commit | 4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770 | [log] [tgz] |
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author | Max Filippov <jcmvbkbc@gmail.com> | Wed Dec 05 07:15:21 2012 +0400 |
committer | Blue Swirl <blauwirbel@gmail.com> | Sat Dec 08 18:48:26 2012 +0000 |
tree | 60e3cc172d4aa177b460d5e72b176a8bd3c95915 | |
parent | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 [diff] |
target-xtensa: implement CACHEATTR SR In XEA1, the Options for Memory Protection and Translation and the corresponding TLB management instructions are not available. Instead, functionality similar to the Region Protection Option is available through the cache attribute register. See ISA, A.2.14 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>