Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging
Accelerators patches
A lot of trivial cleanups and simplifications (moving methods around,
adding/removing #include statements). Most notable changes:
- Rename NEED_CPU_H -> COMPILING_PER_TARGET
- Rename few template headers using the '.h.inc' suffix
- Extract some definitions / declarations into their own header:
- accel/tcg/user-retaddr.h (helper_retaddr)
- include/exec/abi_ptr.h (abi_ptr)
- include/exec/breakpoint.h (CPUBreakpoint, CPUWatchpoint)
- include/exec/mmu-access-type.h (MMUAccessType)
- include/user/tswap-target.h (tswapl, bswaptls)
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# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
* tag 'accel-20240426' of https://github.com/philmd/qemu: (38 commits)
plugins: Include missing 'qemu/bitmap.h' header
hw/core: Avoid including the full 'hw/core/cpu.h' in 'tcg-cpu-ops.h'
exec: Move CPUTLBEntry helpers to cputlb.c
exec: Restrict inclusion of 'user/guest-base.h'
exec: Rename 'exec/user/guest-base.h' as 'user/guest-base.h'
exec: Restrict 'cpu_ldst.h' to TCG accelerator
exec: Restrict TCG specific declarations of 'cputlb.h'
exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header
exec: Declare MMUAccessType type in 'mmu-access-type.h' header
exec: Declare abi_ptr type in its own 'abi_ptr.h' header
exec/user: Do not include 'cpu.h' in 'abitypes.h'
exec: Move [b]tswapl() declarations to 'exec/user/tswap-target.h'
exec: Declare target_words_bigendian() in 'exec/tswap.h'
exec/cpu-all: Remove unused tswapls() definitions
exec/cpu-all: Remove unused 'qemu/thread.h' header
exec/cpu-all: Reduce 'qemu/rcu.h' header inclusion
accel/hvf: Use accel-specific per-vcpu @dirty field
accel/nvmm: Use accel-specific per-vcpu @dirty field
accel/whpx: Use accel-specific per-vcpu @dirty field
accel/tcg: Rename helper-head.h -> helper-head.h.inc
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 96411e6..302b6fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3692,6 +3692,7 @@
M: Riku Voipio <riku.voipio@iki.fi>
S: Maintained
F: accel/tcg/user-exec*.c
+F: include/exec/user/
F: include/user/
F: common-user/
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
index d94d41a..40d4187 100644
--- a/accel/hvf/hvf-accel-ops.c
+++ b/accel/hvf/hvf-accel-ops.c
@@ -204,15 +204,15 @@
static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
{
- if (!cpu->vcpu_dirty) {
+ if (!cpu->accel->dirty) {
hvf_get_registers(cpu);
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
}
}
static void hvf_cpu_synchronize_state(CPUState *cpu)
{
- if (!cpu->vcpu_dirty) {
+ if (!cpu->accel->dirty) {
run_on_cpu(cpu, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL);
}
}
@@ -221,7 +221,7 @@
run_on_cpu_data arg)
{
/* QEMU state is the reference, push it to HVF now and on next entry */
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
}
static void hvf_cpu_synchronize_post_reset(CPUState *cpu)
@@ -402,7 +402,7 @@
#else
r = hv_vcpu_create((hv_vcpuid_t *)&cpu->accel->fd, HV_VCPU_DEFAULT);
#endif
- cpu->vcpu_dirty = 1;
+ cpu->accel->dirty = true;
assert_hvf_ok(r);
cpu->accel->guest_debug_enabled = false;
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
index 8a496a2..dd890d6 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -18,10 +18,6 @@
{
}
-void tlb_set_dirty(CPUState *cpu, vaddr vaddr)
-{
-}
-
int probe_access_flags(CPUArchState *env, vaddr addr, int size,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t retaddr)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 5c70748..225e5fb 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -41,6 +41,9 @@
#include "tb-context.h"
#include "internal-common.h"
#include "internal-target.h"
+#if defined(CONFIG_USER_ONLY)
+#include "user-retaddr.h"
+#endif
/* -icount align implementation. */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 93b1ca8..953c437 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -27,6 +27,9 @@
#include "exec/tb-flush.h"
#include "exec/memory-internal.h"
#include "exec/ram_addr.h"
+#include "exec/mmu-access-type.h"
+#include "exec/tlb-common.h"
+#include "exec/vaddr.h"
#include "tcg/tcg.h"
#include "qemu/error-report.h"
#include "exec/log.h"
@@ -95,6 +98,54 @@
return fast->mask + (1 << CPU_TLB_ENTRY_BITS);
}
+static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
+ MMUAccessType access_type)
+{
+ /* Do not rearrange the CPUTLBEntry structure members. */
+ QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
+ MMU_DATA_LOAD * sizeof(uint64_t));
+ QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
+ MMU_DATA_STORE * sizeof(uint64_t));
+ QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
+ MMU_INST_FETCH * sizeof(uint64_t));
+
+#if TARGET_LONG_BITS == 32
+ /* Use qatomic_read, in case of addr_write; only care about low bits. */
+ const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
+ ptr += HOST_BIG_ENDIAN;
+ return qatomic_read(ptr);
+#else
+ const uint64_t *ptr = &entry->addr_idx[access_type];
+# if TCG_OVERSIZED_GUEST
+ return *ptr;
+# else
+ /* ofs might correspond to .addr_write, so use qatomic_read */
+ return qatomic_read(ptr);
+# endif
+#endif
+}
+
+static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
+{
+ return tlb_read_idx(entry, MMU_DATA_STORE);
+}
+
+/* Find the TLB index corresponding to the mmu_idx + address pair. */
+static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx,
+ vaddr addr)
+{
+ uintptr_t size_mask = cpu->neg.tlb.f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
+
+ return (addr >> TARGET_PAGE_BITS) & size_mask;
+}
+
+/* Find the TLB entry corresponding to the mmu_idx + address pair. */
+static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx,
+ vaddr addr)
+{
+ return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)];
+}
+
static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
size_t max_entries)
{
@@ -1039,7 +1090,7 @@
/* update the TLB corresponding to virtual page vaddr
so that it is no longer dirty */
-void tlb_set_dirty(CPUState *cpu, vaddr addr)
+static void tlb_set_dirty(CPUState *cpu, vaddr addr)
{
int mmu_idx;
diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc
index 97dae70..134da3c 100644
--- a/accel/tcg/ldst_atomicity.c.inc
+++ b/accel/tcg/ldst_atomicity.c.inc
@@ -9,8 +9,8 @@
* See the COPYING file in the top-level directory.
*/
-#include "host/load-extract-al16-al8.h"
-#include "host/store-insert-al16.h"
+#include "host/load-extract-al16-al8.h.inc"
+#include "host/store-insert-al16.h.inc"
#ifdef CONFIG_ATOMIC64
# define HAVE_al8 true
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
index 4ab8553..184bb3e 100644
--- a/accel/tcg/tb-jmp-cache.h
+++ b/accel/tcg/tb-jmp-cache.h
@@ -9,6 +9,9 @@
#ifndef ACCEL_TCG_TB_JMP_CACHE_H
#define ACCEL_TCG_TB_JMP_CACHE_H
+#include "qemu/rcu.h"
+#include "exec/cpu-common.h"
+
#define TB_JMP_CACHE_BITS 12
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 9c957f4..2c7b0cc 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -37,6 +37,8 @@
#include "exec/tb-flush.h"
#include "exec/gdbstub.h"
+#include "hw/core/cpu.h"
+
#include "tcg-accel-ops.h"
#include "tcg-accel-ops-mttcg.h"
#include "tcg-accel-ops-rr.h"
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 9de0bc3..6832e55 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -12,6 +12,7 @@
#include "qemu/error-report.h"
#include "exec/exec-all.h"
#include "exec/translator.h"
+#include "exec/cpu_ldst.h"
#include "exec/plugin-gen.h"
#include "tcg/tcg-op-common.h"
#include "internal-target.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 3cac3a7..1c62147 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -31,6 +31,7 @@
#include "tcg/tcg-ldst.h"
#include "internal-common.h"
#include "internal-target.h"
+#include "user-retaddr.h"
__thread uintptr_t helper_retaddr;
diff --git a/accel/tcg/user-retaddr.h b/accel/tcg/user-retaddr.h
new file mode 100644
index 0000000..e0f57e1
--- /dev/null
+++ b/accel/tcg/user-retaddr.h
@@ -0,0 +1,28 @@
+#ifndef ACCEL_TCG_USER_RETADDR_H
+#define ACCEL_TCG_USER_RETADDR_H
+
+#include "qemu/atomic.h"
+
+extern __thread uintptr_t helper_retaddr;
+
+static inline void set_helper_retaddr(uintptr_t ra)
+{
+ helper_retaddr = ra;
+ /*
+ * Ensure that this write is visible to the SIGSEGV handler that
+ * may be invoked due to a subsequent invalid memory operation.
+ */
+ signal_barrier();
+}
+
+static inline void clear_helper_retaddr(void)
+{
+ /*
+ * Ensure that previous memory operations have succeeded before
+ * removing the data visible to the signal handler.
+ */
+ signal_barrier();
+ helper_retaddr = 0;
+}
+
+#endif
diff --git a/bsd-user/freebsd/target_os_elf.h b/bsd-user/freebsd/target_os_elf.h
index 9df17d5..0112497 100644
--- a/bsd-user/freebsd/target_os_elf.h
+++ b/bsd-user/freebsd/target_os_elf.h
@@ -22,6 +22,7 @@
#include "target_arch_elf.h"
#include "elf.h"
+#include "user/tswap-target.h"
#define bsd_get_ncpu() 1 /* until we pull in bsd-proc.[hc] */
diff --git a/bsd-user/freebsd/target_os_stack.h b/bsd-user/freebsd/target_os_stack.h
index d15fc32..ac0ef22 100644
--- a/bsd-user/freebsd/target_os_stack.h
+++ b/bsd-user/freebsd/target_os_stack.h
@@ -23,6 +23,7 @@
#include <sys/param.h>
#include "target_arch_sigtramp.h"
#include "qemu/guest-random.h"
+#include "user/tswap-target.h"
/*
* The initial FreeBSD stack is as follows:
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 01b3137..29a629d 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -36,6 +36,7 @@
#include "qemu/help_option.h"
#include "qemu/module.h"
#include "exec/exec-all.h"
+#include "user/guest-base.h"
#include "tcg/startup.h"
#include "qemu/timer.h"
#include "qemu/envlist.h"
diff --git a/bsd-user/netbsd/target_os_elf.h b/bsd-user/netbsd/target_os_elf.h
index 2f3cb20..9de0f29 100644
--- a/bsd-user/netbsd/target_os_elf.h
+++ b/bsd-user/netbsd/target_os_elf.h
@@ -22,6 +22,7 @@
#include "target_arch_elf.h"
#include "elf.h"
+#include "user/tswap-target.h"
/* this flag is uneffective under linux too, should be deleted */
#ifndef MAP_DENYWRITE
diff --git a/bsd-user/openbsd/target_os_elf.h b/bsd-user/openbsd/target_os_elf.h
index 6dca9c5..4cf5747 100644
--- a/bsd-user/openbsd/target_os_elf.h
+++ b/bsd-user/openbsd/target_os_elf.h
@@ -22,6 +22,7 @@
#include "target_arch_elf.h"
#include "elf.h"
+#include "user/tswap-target.h"
/* this flag is uneffective under linux too, should be deleted */
#ifndef MAP_DENYWRITE
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index e5a773d..b2faf1d 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu.h"
+#include "user/tswap-target.h"
#include "gdbstub/user.h"
#include "signal-common.h"
#include "trace.h"
diff --git a/bsd-user/strace.c b/bsd-user/strace.c
index 9649975..6dc01d3 100644
--- a/bsd-user/strace.c
+++ b/bsd-user/strace.c
@@ -22,6 +22,7 @@
#include <sys/ioccom.h>
#include "qemu.h"
+#include "user/tswap-target.h"
#include "os-strace.h" /* OS dependent strace print functions */
diff --git a/cpu-target.c b/cpu-target.c
index 4c0621b..f88649c 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -35,6 +35,7 @@
#endif
#include "sysemu/cpus.h"
#include "sysemu/tcg.h"
+#include "exec/tswap.h"
#include "exec/replay-core.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
diff --git a/disas/disas.c b/disas/disas.c
index 7e3b0bb..ec14715 100644
--- a/disas/disas.c
+++ b/disas/disas.c
@@ -6,6 +6,7 @@
#include "disas/disas.h"
#include "disas/capstone.h"
#include "hw/core/cpu.h"
+#include "exec/tswap.h"
#include "exec/memory.h"
/* Filled in by elfload.c. Simplistic, but will do for now. */
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 9c23d44..9c2b8b5 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -37,6 +37,7 @@
#include "hw/cpu/cluster.h"
#include "hw/boards.h"
#endif
+#include "hw/core/cpu.h"
#include "sysemu/hw_accel.h"
#include "sysemu/runstate.h"
diff --git a/host/include/aarch64/host/load-extract-al16-al8.h b/host/include/aarch64/host/load-extract-al16-al8.h.inc
similarity index 100%
rename from host/include/aarch64/host/load-extract-al16-al8.h
rename to host/include/aarch64/host/load-extract-al16-al8.h.inc
diff --git a/host/include/aarch64/host/store-insert-al16.h b/host/include/aarch64/host/store-insert-al16.h.inc
similarity index 100%
rename from host/include/aarch64/host/store-insert-al16.h
rename to host/include/aarch64/host/store-insert-al16.h.inc
diff --git a/host/include/generic/host/load-extract-al16-al8.h b/host/include/generic/host/load-extract-al16-al8.h.inc
similarity index 100%
rename from host/include/generic/host/load-extract-al16-al8.h
rename to host/include/generic/host/load-extract-al16-al8.h.inc
diff --git a/host/include/generic/host/store-insert-al16.h b/host/include/generic/host/store-insert-al16.h.inc
similarity index 100%
rename from host/include/generic/host/store-insert-al16.h
rename to host/include/generic/host/store-insert-al16.h.inc
diff --git a/host/include/loongarch64/host/load-extract-al16-al8.h b/host/include/loongarch64/host/load-extract-al16-al8.h.inc
similarity index 100%
rename from host/include/loongarch64/host/load-extract-al16-al8.h
rename to host/include/loongarch64/host/load-extract-al16-al8.h.inc
diff --git a/host/include/loongarch64/host/store-insert-al16.h b/host/include/loongarch64/host/store-insert-al16.h.inc
similarity index 100%
rename from host/include/loongarch64/host/store-insert-al16.h
rename to host/include/loongarch64/host/store-insert-al16.h.inc
diff --git a/host/include/x86_64/host/load-extract-al16-al8.h b/host/include/x86_64/host/load-extract-al16-al8.h.inc
similarity index 100%
rename from host/include/x86_64/host/load-extract-al16-al8.h
rename to host/include/x86_64/host/load-extract-al16-al8.h.inc
diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c
index c80b58b..6a2ee08 100644
--- a/hw/audio/virtio-snd.c
+++ b/hw/audio/virtio-snd.c
@@ -20,11 +20,11 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "include/qemu/lockable.h"
+#include "exec/tswap.h"
#include "sysemu/runstate.h"
#include "trace.h"
#include "qapi/error.h"
#include "hw/audio/virtio-snd.h"
-#include "hw/core/cpu.h"
#define VIRTIO_SOUND_VM_VERSION 1
#define VIRTIO_SOUND_JACK_DEFAULT 0
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index d0d6a91..2a9a2a4 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/core/cpu.h"
+#include "exec/tswap.h"
#include "hw/core/sysemu-cpu-ops.h"
bool cpu_paging_enabled(const CPUState *cpu)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index d4b5c50..ea8628b 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -31,7 +31,7 @@
*/
#include "qemu/osdep.h"
-#include "hw/core/cpu.h"
+#include "exec/tswap.h"
#include "sysemu/dma.h"
#include "sysemu/reset.h"
#include "hw/boards.h"
diff --git a/hw/display/vga.c b/hw/display/vga.c
index e91a76b..30facc6 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -26,7 +26,7 @@
#include "qemu/units.h"
#include "sysemu/reset.h"
#include "qapi/error.h"
-#include "hw/core/cpu.h"
+#include "exec/tswap.h"
#include "hw/display/vga.h"
#include "hw/i386/x86.h"
#include "hw/pci/pci.h"
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 871674f..893a072 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -20,6 +20,7 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
+#include "exec/tswap.h"
#include "qom/object_interfaces.h"
#include "hw/core/cpu.h"
#include "hw/virtio/virtio.h"
diff --git a/include/exec/abi_ptr.h b/include/exec/abi_ptr.h
new file mode 100644
index 0000000..2aedcce
--- /dev/null
+++ b/include/exec/abi_ptr.h
@@ -0,0 +1,33 @@
+/*
+ * QEMU abi_ptr type definitions
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef EXEC_ABI_PTR_H
+#define EXEC_ABI_PTR_H
+
+#include "cpu-param.h"
+
+#if defined(CONFIG_USER_ONLY)
+/*
+ * sparc32plus has 64bit long but 32bit space address
+ * this can make bad result with g2h() and h2g()
+ */
+#if TARGET_VIRT_ADDR_SPACE_BITS <= 32
+typedef uint32_t abi_ptr;
+#define TARGET_ABI_FMT_ptr "%x"
+#else
+typedef uint64_t abi_ptr;
+#define TARGET_ABI_FMT_ptr "%"PRIx64
+#endif
+
+#else /* !CONFIG_USER_ONLY */
+
+#include "exec/target_long.h"
+
+typedef target_ulong abi_ptr;
+#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
+
+#endif /* !CONFIG_USER_ONLY */
+
+#endif
diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h
new file mode 100644
index 0000000..95f0482
--- /dev/null
+++ b/include/exec/breakpoint.h
@@ -0,0 +1,30 @@
+/*
+ * QEMU breakpoint & watchpoint definitions
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef EXEC_BREAKPOINT_H
+#define EXEC_BREAKPOINT_H
+
+#include "qemu/queue.h"
+#include "exec/vaddr.h"
+#include "exec/memattrs.h"
+
+typedef struct CPUBreakpoint {
+ vaddr pc;
+ int flags; /* BP_* */
+ QTAILQ_ENTRY(CPUBreakpoint) entry;
+} CPUBreakpoint;
+
+typedef struct CPUWatchpoint {
+ vaddr vaddr;
+ vaddr len;
+ vaddr hitaddr;
+ MemTxAttrs hitattrs;
+ int flags; /* BP_* */
+ QTAILQ_ENTRY(CPUWatchpoint) entry;
+} CPUWatchpoint;
+
+#endif
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 1a6510f..e75ec13 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -22,9 +22,7 @@
#include "exec/cpu-common.h"
#include "exec/memory.h"
#include "exec/tswap.h"
-#include "qemu/thread.h"
#include "hw/core/cpu.h"
-#include "qemu/rcu.h"
/* some important defines:
*
@@ -38,16 +36,6 @@
#define BSWAP_NEEDED
#endif
-#if TARGET_LONG_SIZE == 4
-#define tswapl(s) tswap32(s)
-#define tswapls(s) tswap32s((uint32_t *)(s))
-#define bswaptls(s) bswap32s(s)
-#else
-#define tswapl(s) tswap64(s)
-#define tswapls(s) tswap64s((uint64_t *)(s))
-#define bswaptls(s) bswap64s(s)
-#endif
-
/* Target-endianness CPU memory access functions. These fit into the
* {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
*/
@@ -77,9 +65,6 @@
#if defined(CONFIG_USER_ONLY)
#include "exec/user/abitypes.h"
-#include "exec/user/guest-base.h"
-
-extern bool have_guest_base;
/*
* If non-zero, the guest virtual address space is a contiguous subset
@@ -391,6 +376,7 @@
#endif /* !CONFIG_USER_ONLY */
/* Validate correct placement of CPUArchState. */
+#include "cpu.h"
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 3915438..0dbef30 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -19,7 +19,7 @@
#ifndef CPU_DEFS_H
#define CPU_DEFS_H
-#ifndef NEED_CPU_H
+#ifndef COMPILING_PER_TARGET
#error cpu.h included from common code
#endif
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index eb8f3f0..11ba377 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -1,5 +1,5 @@
/*
- * Software MMU support
+ * Software MMU support (per-target)
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -62,21 +62,18 @@
#ifndef CPU_LDST_H
#define CPU_LDST_H
+#ifndef CONFIG_TCG
+#error Can only include this header with TCG
+#endif
+
#include "exec/memopidx.h"
+#include "exec/abi_ptr.h"
+#include "exec/mmu-access-type.h"
#include "qemu/int128.h"
-#include "cpu.h"
#if defined(CONFIG_USER_ONLY)
-/* sparc32plus has 64bit long but 32bit space address
- * this can make bad result with g2h() and h2g()
- */
-#if TARGET_VIRT_ADDR_SPACE_BITS <= 32
-typedef uint32_t abi_ptr;
-#define TARGET_ABI_FMT_ptr "%x"
-#else
-typedef uint64_t abi_ptr;
-#define TARGET_ABI_FMT_ptr "%"PRIx64
-#endif
+
+#include "user/guest-base.h"
#ifndef TARGET_TAGGED_ADDRESSES
static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x)
@@ -120,10 +117,8 @@
assert(h2g_valid(x)); \
h2g_nocheck(x); \
})
-#else
-typedef vaddr abi_ptr;
-#define TARGET_ABI_FMT_ptr VADDR_PRIx
-#endif
+
+#endif /* CONFIG_USER_ONLY */
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
@@ -300,84 +295,6 @@
Int128 cmpv, Int128 newv,
MemOpIdx oi, uintptr_t retaddr);
-#if defined(CONFIG_USER_ONLY)
-
-extern __thread uintptr_t helper_retaddr;
-
-static inline void set_helper_retaddr(uintptr_t ra)
-{
- helper_retaddr = ra;
- /*
- * Ensure that this write is visible to the SIGSEGV handler that
- * may be invoked due to a subsequent invalid memory operation.
- */
- signal_barrier();
-}
-
-static inline void clear_helper_retaddr(void)
-{
- /*
- * Ensure that previous memory operations have succeeded before
- * removing the data visible to the signal handler.
- */
- signal_barrier();
- helper_retaddr = 0;
-}
-
-#else
-
-#include "tcg/oversized-guest.h"
-
-static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
- MMUAccessType access_type)
-{
- /* Do not rearrange the CPUTLBEntry structure members. */
- QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
- MMU_DATA_LOAD * sizeof(uint64_t));
- QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
- MMU_DATA_STORE * sizeof(uint64_t));
- QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
- MMU_INST_FETCH * sizeof(uint64_t));
-
-#if TARGET_LONG_BITS == 32
- /* Use qatomic_read, in case of addr_write; only care about low bits. */
- const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
- ptr += HOST_BIG_ENDIAN;
- return qatomic_read(ptr);
-#else
- const uint64_t *ptr = &entry->addr_idx[access_type];
-# if TCG_OVERSIZED_GUEST
- return *ptr;
-# else
- /* ofs might correspond to .addr_write, so use qatomic_read */
- return qatomic_read(ptr);
-# endif
-#endif
-}
-
-static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
-{
- return tlb_read_idx(entry, MMU_DATA_STORE);
-}
-
-/* Find the TLB index corresponding to the mmu_idx + address pair. */
-static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx,
- vaddr addr)
-{
- uintptr_t size_mask = cpu->neg.tlb.f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
-
- return (addr >> TARGET_PAGE_BITS) & size_mask;
-}
-
-/* Find the TLB entry corresponding to the mmu_idx + address pair. */
-static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx,
- vaddr addr)
-{
- return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)];
-}
-
-#endif /* defined(CONFIG_USER_ONLY) */
-
#if TARGET_BIG_ENDIAN
# define cpu_lduw_data cpu_lduw_be_data
# define cpu_ldsw_data cpu_ldsw_be_data
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index 6da1462..ef18642 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -22,9 +22,14 @@
#include "exec/cpu-common.h"
+#ifdef CONFIG_TCG
+
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
void tlb_protect_code(ram_addr_t ram_addr);
void tlb_unprotect_code(ram_addr_t ram_addr);
#endif
+
+#endif /* CONFIG_TCG */
+
#endif
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 3e53501..4c5e470 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -22,8 +22,10 @@
#include "cpu.h"
#if defined(CONFIG_USER_ONLY)
+#include "exec/abi_ptr.h"
#include "exec/cpu_ldst.h"
#endif
+#include "exec/mmu-access-type.h"
#include "exec/translation-block.h"
#include "qemu/clang-tsa.h"
@@ -654,7 +656,6 @@
#define WITH_MMAP_LOCK_GUARD()
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
-void tlb_set_dirty(CPUState *cpu, vaddr addr);
void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
MemoryRegionSection *
diff --git a/include/exec/helper-gen.h.inc b/include/exec/helper-gen.h.inc
index c009641..d9fd3ed 100644
--- a/include/exec/helper-gen.h.inc
+++ b/include/exec/helper-gen.h.inc
@@ -8,7 +8,7 @@
#include "tcg/tcg.h"
#include "tcg/helper-info.h"
-#include "exec/helper-head.h"
+#include "exec/helper-head.h.inc"
#define DEF_HELPER_FLAGS_0(name, flags, ret) \
extern TCGHelperInfo glue(helper_info_, name); \
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h.inc
similarity index 98%
rename from include/exec/helper-head.h
rename to include/exec/helper-head.h.inc
index 28ceab0..5ef467a 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h.inc
@@ -43,7 +43,7 @@
#define dh_ctype_noreturn G_NORETURN void
#define dh_ctype(t) dh_ctype_##t
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
# ifdef TARGET_LONG_BITS
# if TARGET_LONG_BITS == 32
# define dh_alias_tl i32
@@ -54,7 +54,7 @@
# endif
# endif
# define dh_ctype_tl target_ulong
-#endif
+#endif /* COMPILING_PER_TARGET */
/* We can't use glue() here because it falls foul of C preprocessor
recursive expansion rules. */
diff --git a/include/exec/helper-info.c.inc b/include/exec/helper-info.c.inc
index 530d2e6..c551736 100644
--- a/include/exec/helper-info.c.inc
+++ b/include/exec/helper-info.c.inc
@@ -7,7 +7,7 @@
#include "tcg/tcg.h"
#include "tcg/helper-info.h"
-#include "exec/helper-head.h"
+#include "exec/helper-head.h.inc"
/*
* Need one more level of indirection before stringification
diff --git a/include/exec/helper-proto.h.inc b/include/exec/helper-proto.h.inc
index c3aa666..f8e57e4 100644
--- a/include/exec/helper-proto.h.inc
+++ b/include/exec/helper-proto.h.inc
@@ -5,7 +5,7 @@
* Define HELPER_H for the header file to be expanded.
*/
-#include "exec/helper-head.h"
+#include "exec/helper-head.h.inc"
/*
* Work around an issue with --enable-lto, in which GCC's ipa-split pass
diff --git a/include/exec/memop.h b/include/exec/memop.h
index a86dc67..06417ff 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -35,7 +35,7 @@
MO_LE = 0,
MO_BE = MO_BSWAP,
#endif
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#if TARGET_BIG_ENDIAN
MO_TE = MO_BE,
#else
@@ -135,7 +135,7 @@
MO_BESL = MO_BE | MO_SL,
MO_BESQ = MO_BE | MO_SQ,
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
MO_TEUW = MO_TE | MO_UW,
MO_TEUL = MO_TE | MO_UL,
MO_TEUQ = MO_TE | MO_UQ,
diff --git a/include/exec/memory.h b/include/exec/memory.h
index dbb1bad..dadb5cd 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -3107,7 +3107,7 @@
MemTxResult address_space_set(AddressSpace *as, hwaddr addr,
uint8_t c, hwaddr len, MemTxAttrs attrs);
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
/* enum device_endian to MemOp. */
static inline MemOp devend_memop(enum device_endian end)
{
@@ -3125,7 +3125,7 @@
return (end == non_host_endianness) ? MO_BSWAP : 0;
#endif
}
-#endif
+#endif /* COMPILING_PER_TARGET */
/*
* Inhibit technologies that require discarding of pages in RAM blocks, e.g.,
diff --git a/include/exec/mmu-access-type.h b/include/exec/mmu-access-type.h
new file mode 100644
index 0000000..28bbb05
--- /dev/null
+++ b/include/exec/mmu-access-type.h
@@ -0,0 +1,18 @@
+/*
+ * QEMU MMU Access type definitions
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef EXEC_MMU_ACCESS_TYPE_H
+#define EXEC_MMU_ACCESS_TYPE_H
+
+typedef enum MMUAccessType {
+ MMU_DATA_LOAD = 0,
+ MMU_DATA_STORE = 1,
+ MMU_INST_FETCH = 2
+#define MMU_ACCESS_COUNT 3
+} MMUAccessType;
+
+#endif
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 07c8f86..891c44c 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -26,6 +26,7 @@
#include "exec/ramlist.h"
#include "exec/ramblock.h"
#include "exec/exec-all.h"
+#include "qemu/rcu.h"
extern uint64_t total_dirty_pages;
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 2c4fb81..6cd937a 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -19,7 +19,10 @@
*/
#include "qemu/bswap.h"
-#include "exec/cpu_ldst.h" /* for abi_ptr */
+#include "exec/cpu-common.h"
+#include "exec/cpu-defs.h"
+#include "exec/abi_ptr.h"
+#include "cpu.h"
/**
* gen_intermediate_code
diff --git a/include/exec/tswap.h b/include/exec/tswap.h
index 68944a8..b7a4191 100644
--- a/include/exec/tswap.h
+++ b/include/exec/tswap.h
@@ -8,18 +8,28 @@
#ifndef TSWAP_H
#define TSWAP_H
-#include "hw/core/cpu.h"
#include "qemu/bswap.h"
+/**
+ * target_words_bigendian:
+ * Returns true if the (default) endianness of the target is big endian,
+ * false otherwise. Note that in target-specific code, you can use
+ * TARGET_BIG_ENDIAN directly instead. On the other hand, common
+ * code should normally never need to know about the endianness of the
+ * target, so please do *not* use this function unless you know very well
+ * what you are doing!
+ */
+bool target_words_bigendian(void);
+
/*
* If we're in target-specific code, we can hard-code the swapping
* condition, otherwise we have to do (slower) run-time checks.
*/
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#define target_needs_bswap() (HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN)
#else
#define target_needs_bswap() (target_words_bigendian() != HOST_BIG_ENDIAN)
-#endif
+#endif /* COMPILING_PER_TARGET */
static inline uint16_t tswap16(uint16_t s)
{
diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h
index db4a670..3ec1969 100644
--- a/include/exec/user/abitypes.h
+++ b/include/exec/user/abitypes.h
@@ -1,7 +1,13 @@
#ifndef EXEC_USER_ABITYPES_H
#define EXEC_USER_ABITYPES_H
-#include "cpu.h"
+#ifndef CONFIG_USER_ONLY
+#error Cannot include this header from system emulation
+#endif
+
+#include "exec/cpu-defs.h"
+#include "exec/tswap.h"
+#include "user/tswap-target.h"
#ifdef TARGET_ABI32
#define TARGET_ABI_BITS 32
diff --git a/include/exec/user/guest-base.h b/include/exec/user/guest-base.h
deleted file mode 100644
index afe2ab7..0000000
--- a/include/exec/user/guest-base.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: LGPL-2.1-or-later */
-/*
- * Declaration of guest_base.
- * Copyright (c) 2003 Fabrice Bellard
- */
-
-#ifndef EXEC_USER_GUEST_BASE_H
-#define EXEC_USER_GUEST_BASE_H
-
-extern uintptr_t guest_base;
-
-#endif
diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h
index c573aef..26140ef 100644
--- a/include/gdbstub/helpers.h
+++ b/include/gdbstub/helpers.h
@@ -12,8 +12,12 @@
#ifndef _GDBSTUB_HELPERS_H_
#define _GDBSTUB_HELPERS_H_
-#ifdef NEED_CPU_H
-#include "cpu.h"
+#ifndef COMPILING_PER_TARGET
+#error "gdbstub helpers should only be included by target specific code"
+#endif
+
+#include "exec/tswap.h"
+#include "cpu-param.h"
/*
* The GDB remote protocol transfers values in target byte order. As
@@ -96,8 +100,4 @@
#define ldtul_p(addr) ldl_p(addr)
#endif
-#else
-#error "gdbstub helpers should only be included by target specific code"
-#endif
-
#endif /* _GDBSTUB_HELPERS_H_ */
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index ec14f74..46b99a7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -22,9 +22,11 @@
#include "hw/qdev-core.h"
#include "disas/dis-asm.h"
+#include "exec/breakpoint.h"
#include "exec/hwaddr.h"
#include "exec/vaddr.h"
#include "exec/memattrs.h"
+#include "exec/mmu-access-type.h"
#include "exec/tlb-common.h"
#include "qapi/qapi-types-run-state.h"
#include "qemu/bitmap.h"
@@ -80,13 +82,6 @@
typedef struct ArchCPU CpuInstanceType; \
OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
-typedef enum MMUAccessType {
- MMU_DATA_LOAD = 0,
- MMU_DATA_STORE = 1,
- MMU_INST_FETCH = 2
-#define MMU_ACCESS_COUNT 3
-} MMUAccessType;
-
typedef struct CPUWatchpoint CPUWatchpoint;
/* see accel-cpu.h */
@@ -353,21 +348,6 @@
bool can_do_io;
} CPUNegativeOffsetState;
-typedef struct CPUBreakpoint {
- vaddr pc;
- int flags; /* BP_* */
- QTAILQ_ENTRY(CPUBreakpoint) entry;
-} CPUBreakpoint;
-
-struct CPUWatchpoint {
- vaddr vaddr;
- vaddr len;
- vaddr hitaddr;
- MemTxAttrs hitattrs;
- int flags; /* BP_* */
- QTAILQ_ENTRY(CPUWatchpoint) entry;
-};
-
struct KVMState;
struct kvm_run;
@@ -525,6 +505,7 @@
uint32_t kvm_fetch_index;
uint64_t dirty_pages;
int kvm_vcpu_stats_fd;
+ bool vcpu_dirty;
/* Use by accel-block: CPU is executing an ioctl() */
QemuLockCnt in_ioctl_lock;
@@ -546,8 +527,6 @@
int32_t exception_index;
AccelCPUState *accel;
- /* shared by kvm and hvf */
- bool vcpu_dirty;
/* Used to keep track of an outstanding cpu throttle thread for migration
* autoconverge
@@ -1169,20 +1148,9 @@
void cpu_exec_unrealizefn(CPUState *cpu);
void cpu_exec_reset_hold(CPUState *cpu);
-/**
- * target_words_bigendian:
- * Returns true if the (default) endianness of the target is big endian,
- * false otherwise. Note that in target-specific code, you can use
- * TARGET_BIG_ENDIAN directly instead. On the other hand, common
- * code should normally never need to know about the endianness of the
- * target, so please do *not* use this function unless you know very well
- * what you are doing!
- */
-bool target_words_bigendian(void);
-
const char *target_name(void);
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#ifndef CONFIG_USER_ONLY
@@ -1197,7 +1165,7 @@
}
#endif /* !CONFIG_USER_ONLY */
-#endif /* NEED_CPU_H */
+#endif /* COMPILING_PER_TARGET */
#define UNASSIGNED_CPU_INDEX -1
#define UNASSIGNED_CLUSTER_INDEX -1
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index dc1f16a..9387d38 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -10,7 +10,11 @@
#ifndef TCG_CPU_OPS_H
#define TCG_CPU_OPS_H
-#include "hw/core/cpu.h"
+#include "exec/breakpoint.h"
+#include "exec/hwaddr.h"
+#include "exec/memattrs.h"
+#include "exec/mmu-access-type.h"
+#include "exec/vaddr.h"
struct TCGCPUOps {
/**
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index c7053cd..f61edcf 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -32,7 +32,7 @@
#endif
#include "config-host.h"
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#include CONFIG_TARGET
#else
#include "exec/poison.h"
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
index 12a96ce..41db748 100644
--- a/include/qemu/plugin.h
+++ b/include/qemu/plugin.h
@@ -13,6 +13,7 @@
#include "qemu/queue.h"
#include "qemu/option.h"
#include "qemu/plugin-event.h"
+#include "qemu/bitmap.h"
#include "exec/memopidx.h"
#include "hw/core/cpu.h"
diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h
index 3963eaf..dd289af 100644
--- a/include/semihosting/uaccess.h
+++ b/include/semihosting/uaccess.h
@@ -14,7 +14,9 @@
#error Cannot include semihosting/uaccess.h from user emulation
#endif
-#include "cpu.h"
+#include "exec/cpu-common.h"
+#include "exec/cpu-defs.h"
+#include "exec/tswap.h"
#define get_user_u64(val, addr) \
({ uint64_t val_ = 0; \
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index 4a7c6af..730f927 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -16,7 +16,7 @@
#include "qemu/accel.h"
#include "qom/object.h"
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#include "cpu.h"
#ifdef CONFIG_HVF
@@ -26,7 +26,7 @@
#define hvf_enabled() 0
#endif /* !CONFIG_HVF */
-#endif /* NEED_CPU_H */
+#endif /* COMPILING_PER_TARGET */
#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
@@ -34,7 +34,7 @@
DECLARE_INSTANCE_CHECKER(HVFState, HVF_STATE,
TYPE_HVF_ACCEL)
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
struct hvf_sw_breakpoint {
vaddr pc;
vaddr saved_insn;
@@ -66,6 +66,6 @@
* Return whether the guest supports debugging.
*/
bool hvf_arch_supports_guest_debug(void);
-#endif /* NEED_CPU_H */
+#endif /* COMPILING_PER_TARGET */
#endif
diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
index 718bedd..4a327fd 100644
--- a/include/sysemu/hvf_int.h
+++ b/include/sysemu/hvf_int.h
@@ -55,6 +55,7 @@
bool vtimer_masked;
sigset_t unblock_ipi_mask;
bool guest_debug_enabled;
+ bool dirty;
};
void assert_hvf_ok(hv_return_t ret);
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 47f9e8b..eaf801b 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -20,7 +20,7 @@
#include "qemu/accel.h"
#include "qom/object.h"
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
# ifdef CONFIG_KVM
# include <linux/kvm.h>
# define CONFIG_KVM_IS_POSSIBLE
@@ -210,7 +210,7 @@
int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
int kvm_on_sigbus(int code, void *addr);
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#include "cpu.h"
void kvm_flush_coalesced_mmio_buffer(void);
@@ -435,7 +435,7 @@
int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,
hwaddr *phys_addr);
-#endif /* NEED_CPU_H */
+#endif /* COMPILING_PER_TARGET */
void kvm_cpu_synchronize_state(CPUState *cpu);
diff --git a/include/sysemu/nvmm.h b/include/sysemu/nvmm.h
index be7bc9a..6971ddb 100644
--- a/include/sysemu/nvmm.h
+++ b/include/sysemu/nvmm.h
@@ -12,7 +12,7 @@
#ifndef QEMU_NVMM_H
#define QEMU_NVMM_H
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#ifdef CONFIG_NVMM
@@ -24,6 +24,6 @@
#endif /* CONFIG_NVMM */
-#endif /* NEED_CPU_H */
+#endif /* COMPILING_PER_TARGET */
#endif /* QEMU_NVMM_H */
diff --git a/include/sysemu/whpx.h b/include/sysemu/whpx.h
index 781ca5b..00ff409 100644
--- a/include/sysemu/whpx.h
+++ b/include/sysemu/whpx.h
@@ -15,7 +15,7 @@
#ifndef QEMU_WHPX_H
#define QEMU_WHPX_H
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#ifdef CONFIG_WHPX
@@ -29,6 +29,6 @@
#endif /* CONFIG_WHPX */
-#endif /* NEED_CPU_H */
+#endif /* COMPILING_PER_TARGET */
#endif /* QEMU_WHPX_H */
diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h
index a9f591f..754ec2e6 100644
--- a/include/sysemu/xen.h
+++ b/include/sysemu/xen.h
@@ -16,13 +16,13 @@
#include "exec/cpu-common.h"
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
# ifdef CONFIG_XEN
# define CONFIG_XEN_IS_POSSIBLE
# endif
#else
# define CONFIG_XEN_IS_POSSIBLE
-#endif
+#endif /* COMPILING_PER_TARGET */
#ifdef CONFIG_XEN_IS_POSSIBLE
diff --git a/include/user/guest-base.h b/include/user/guest-base.h
new file mode 100644
index 0000000..055c1d1
--- /dev/null
+++ b/include/user/guest-base.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: LGPL-2.1-or-later */
+/*
+ * Declaration of guest_base.
+ * Copyright (c) 2003 Fabrice Bellard
+ */
+
+#ifndef USER_GUEST_BASE_H
+#define USER_GUEST_BASE_H
+
+#ifndef CONFIG_USER_ONLY
+#error Cannot include this header from system emulation
+#endif
+
+extern uintptr_t guest_base;
+
+extern bool have_guest_base;
+
+#endif
diff --git a/include/user/tswap-target.h b/include/user/tswap-target.h
new file mode 100644
index 0000000..4719330
--- /dev/null
+++ b/include/user/tswap-target.h
@@ -0,0 +1,22 @@
+/*
+ * target-specific swap() definitions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef USER_TSWAP_H
+#define USER_TSWAP_H
+
+#include "exec/cpu-defs.h"
+#include "exec/tswap.h"
+
+#if TARGET_LONG_SIZE == 4
+#define tswapl(s) tswap32(s)
+#define bswaptls(s) bswap32s(s)
+#else
+#define tswapl(s) tswap64(s)
+#define bswaptls(s) bswap64s(s)
+#endif
+
+#endif
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index a0999da..f9461d2 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -7,6 +7,8 @@
#include <sys/shm.h>
#include "qemu.h"
+#include "user/tswap-target.h"
+#include "user/guest-base.h"
#include "user-internals.h"
#include "signal-common.h"
#include "loader.h"
diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c
index cfe70fc..990048f 100644
--- a/linux-user/i386/signal.c
+++ b/linux-user/i386/signal.c
@@ -21,6 +21,7 @@
#include "user-internals.h"
#include "signal-common.h"
#include "linux-user/trace.h"
+#include "user/tswap-target.h"
/* from the Linux kernel - /arch/x86/include/uapi/asm/sigcontext.h */
diff --git a/linux-user/main.c b/linux-user/main.c
index 149e354..94e4c47 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -38,6 +38,7 @@
#include "qemu/help_option.h"
#include "qemu/module.h"
#include "qemu/plugin.h"
+#include "user/guest-base.h"
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
#include "gdbstub/user.h"
diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c
index 652038a..a1d8c0b 100644
--- a/linux-user/ppc/signal.c
+++ b/linux-user/ppc/signal.c
@@ -21,6 +21,7 @@
#include "user-internals.h"
#include "signal-common.h"
#include "linux-user/trace.h"
+#include "user/tswap-target.h"
#include "vdso-asmoffset.h"
/* See arch/powerpc/include/asm/ucontext.h. Only used for 32-bit PPC;
diff --git a/meson.build b/meson.build
index 553b940..5db2dbc 100644
--- a/meson.build
+++ b/meson.build
@@ -3523,7 +3523,7 @@
pagevary = declare_dependency(link_with: pagevary)
endif
common_ss.add(pagevary)
-specific_ss.add(files('page-vary-target.c'))
+specific_ss.add(files('page-target.c', 'page-vary-target.c'))
subdir('backends')
subdir('disas')
@@ -3610,7 +3610,7 @@
if target.endswith('-softmmu')
config_target = config_target_mak[target]
target_inc = [include_directories('target' / config_target['TARGET_BASE_ARCH'])]
- c_args = ['-DNEED_CPU_H',
+ c_args = ['-DCOMPILING_PER_TARGET',
'-DCONFIG_TARGET="@0@-config-target.h"'.format(target),
'-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)]
target_module_ss = module_ss.apply(config_target, strict: false)
@@ -3793,7 +3793,7 @@
target_base_arch = config_target['TARGET_BASE_ARCH']
arch_srcs = [config_target_h[target]]
arch_deps = []
- c_args = ['-DNEED_CPU_H',
+ c_args = ['-DCOMPILING_PER_TARGET',
'-DCONFIG_TARGET="@0@-config-target.h"'.format(target),
'-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)]
link_args = emulator_link_args
diff --git a/page-target.c b/page-target.c
new file mode 100644
index 0000000..82211c8
--- /dev/null
+++ b/page-target.c
@@ -0,0 +1,44 @@
+/*
+ * QEMU page values getters (target independent)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "exec/target_page.h"
+#include "exec/cpu-defs.h"
+#include "cpu.h"
+#include "exec/cpu-all.h"
+
+size_t qemu_target_page_size(void)
+{
+ return TARGET_PAGE_SIZE;
+}
+
+int qemu_target_page_mask(void)
+{
+ return TARGET_PAGE_MASK;
+}
+
+int qemu_target_page_bits(void)
+{
+ return TARGET_PAGE_BITS;
+}
+
+int qemu_target_page_bits_min(void)
+{
+ return TARGET_PAGE_BITS_MIN;
+}
+
+/* Convert target pages to MiB (2**20). */
+size_t qemu_target_pages_to_MiB(size_t pages)
+{
+ int page_bits = TARGET_PAGE_BITS;
+
+ /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */
+ g_assert(page_bits < 20);
+
+ return pages >> (20 - page_bits);
+}
diff --git a/scripts/analyze-inclusions b/scripts/analyze-inclusions
index 45c821d..b6280f2 100644
--- a/scripts/analyze-inclusions
+++ b/scripts/analyze-inclusions
@@ -92,7 +92,7 @@
analyze -include ../include/qemu/osdep.h trace/generated-tracers.h
echo target/i386/cpu.h:
-analyze -DNEED_CPU_H -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../target/i386/cpu.h
+analyze -DCOMPILING_PER_TARGET -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../target/i386/cpu.h
-echo hw/hw.h + NEED_CPU_H:
-analyze -DNEED_CPU_H -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../include/hw/hw.h
+echo hw/hw.h + COMPILING_PER_TARGET:
+analyze -DCOMPILING_PER_TARGET -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../include/hw/hw.h
diff --git a/semihosting/guestfd.c b/semihosting/guestfd.c
index 955c2ef..d324143 100644
--- a/semihosting/guestfd.c
+++ b/semihosting/guestfd.c
@@ -12,10 +12,7 @@
#include "gdbstub/syscalls.h"
#include "semihosting/semihost.h"
#include "semihosting/guestfd.h"
-#ifdef CONFIG_USER_ONLY
-#include "qemu.h"
-#else
-#include "semihosting/uaccess.h"
+#ifndef CONFIG_USER_ONLY
#include CONFIG_DEVICES
#endif
diff --git a/system/physmem.c b/system/physmem.c
index c3d04ca..1a81c22 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -3540,36 +3540,6 @@
return 0;
}
-/*
- * Allows code that needs to deal with migration bitmaps etc to still be built
- * target independent.
- */
-size_t qemu_target_page_size(void)
-{
- return TARGET_PAGE_SIZE;
-}
-
-int qemu_target_page_bits(void)
-{
- return TARGET_PAGE_BITS;
-}
-
-int qemu_target_page_bits_min(void)
-{
- return TARGET_PAGE_BITS_MIN;
-}
-
-/* Convert target pages to MiB (2**20). */
-size_t qemu_target_pages_to_MiB(size_t pages)
-{
- int page_bits = TARGET_PAGE_BITS;
-
- /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */
- g_assert(page_bits < 20);
-
- return pages >> (20 - page_bits);
-}
-
bool cpu_physical_memory_is_io(hwaddr phys_addr)
{
MemoryRegion*mr;
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index c969cb0..5ce213a 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -27,4 +27,7 @@
# define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#endif
+/* Alpha processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 7188a40..f9e2ecb 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -24,9 +24,6 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
-/* Alpha processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index da3243a..2d5f3aa 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -27,14 +27,16 @@
# else
# define TARGET_PAGE_BITS 12
# endif
-#else
+#else /* !CONFIG_USER_ONLY */
/*
* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
* have to support 1K tiny pages.
*/
# define TARGET_PAGE_BITS_VARY
# define TARGET_PAGE_BITS_MIN 10
+#endif /* !CONFIG_USER_ONLY */
-#endif
+/* ARM processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 97997db..17efc5d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,9 +30,6 @@
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
-/* ARM processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
#ifdef TARGET_AARCH64
#define KVM_HAVE_MCE_INJECTION 1
#endif
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 65a5601..db628c1 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -806,9 +806,9 @@
static void flush_cpu_state(CPUState *cpu)
{
- if (cpu->vcpu_dirty) {
+ if (cpu->accel->dirty) {
hvf_put_registers(cpu);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
}
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b53f5e8..e40ec45 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -25,6 +25,7 @@
#ifndef TARGET_ARM_INTERNALS_H
#define TARGET_ARM_INTERNALS_H
+#include "exec/breakpoint.h"
#include "hw/registerfields.h"
#include "tcg/tcg-gvec-desc.h"
#include "syndrome.h"
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index 7c6adc1..c44d23d 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -14,13 +14,13 @@
#ifndef ARM_KVM_CONSTS_H
#define ARM_KVM_CONSTS_H
-#ifdef NEED_CPU_H
+#ifdef COMPILING_PER_TARGET
#ifdef CONFIG_KVM
#include <linux/kvm.h>
#include <linux/psci.h>
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
#endif
-#endif
+#endif /* COMPILING_PER_TARGET */
#ifndef MISMATCH_CHECK
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 9a92bc7..93c2f47 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -32,4 +32,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define TCG_GUEST_DEFAULT_MO 0
+
#endif
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d185d20..4725535 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -30,8 +30,6 @@
#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
-#define TCG_GUEST_DEFAULT_MO 0
-
/*
* AVR has two memory spaces, data & code.
* e.g. both have 0 address
diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c
index 2eeee2b..d6d3c14 100644
--- a/target/avr/gdbstub.c
+++ b/target/avr/gdbstub.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "gdbstub/helpers.h"
+#include "cpu.h"
int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index f163eef..47a870f 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -23,6 +23,7 @@
#include "exec/helper-gen.h"
#include "exec/helper-proto.h"
#include "exec/translation-block.h"
+#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "internal.h"
#include "attribs.h"
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index bb3d7ef..473d489 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -21,4 +21,12 @@
#define TARGET_PAGE_BITS 12
+/* PA-RISC 1.x processors have a strong memory model. */
+/*
+ * ??? While we do not yet implement PA-RISC 2.0, those processors have
+ * a weak memory model, but with TLB bits that force ordering on a per-page
+ * basis. It's probably easier to fall back to a strong memory model.
+ */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index a072d0b..fb2e4c4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -25,12 +25,6 @@
#include "qemu/cpu-float.h"
#include "qemu/interval-tree.h"
-/* PA-RISC 1.x processors have a strong memory model. */
-/* ??? While we do not yet implement PA-RISC 2.0, those processors have
- a weak memory model, but with TLB bits that force ordering on a per-page
- basis. It's probably easier to fall back to a strong memory model. */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#define MMU_ABS_W_IDX 6
#define MMU_ABS_IDX 7
#define MMU_KERNEL_IDX 8
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index 911b4cd..5e15335 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -24,4 +24,7 @@
#endif
#define TARGET_PAGE_BITS 12
+/* The x86 has a strong memory model with some store-after-load re-ordering */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
#endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6112e27..565c7a9 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -30,9 +30,6 @@
#define XEN_NR_VIRQS 24
-/* The x86 has a strong memory model with some store-after-load re-ordering */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
#define KVM_HAVE_MCE_INJECTION 1
/* support for self modifying code even if the modified instruction is
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index 1ed8ed5..e493452 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -419,9 +419,9 @@
}
do {
- if (cpu->vcpu_dirty) {
+ if (cpu->accel->dirty) {
hvf_put_registers(cpu);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
if (hvf_inject_interrupts(cpu)) {
diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c
index be2c462..1569f86 100644
--- a/target/i386/hvf/x86hvf.c
+++ b/target/i386/hvf/x86hvf.c
@@ -427,7 +427,7 @@
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- if (!cs->vcpu_dirty) {
+ if (!cs->accel->dirty) {
/* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */
env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
}
diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c
index 49a3a3b..f9cced5 100644
--- a/target/i386/nvmm/nvmm-all.c
+++ b/target/i386/nvmm/nvmm-all.c
@@ -30,6 +30,7 @@
struct nvmm_vcpu vcpu;
uint8_t tpr;
bool stop;
+ bool dirty;
/* Window-exiting for INTs/NMIs. */
bool int_window_exit;
@@ -507,7 +508,7 @@
}
/* Needed, otherwise infinite loop. */
- current_cpu->vcpu_dirty = false;
+ current_cpu->accel->dirty = false;
}
static void
@@ -516,7 +517,7 @@
cpu_physical_memory_rw(mem->gpa, mem->data, mem->size, mem->write);
/* Needed, otherwise infinite loop. */
- current_cpu->vcpu_dirty = false;
+ current_cpu->accel->dirty = false;
}
static struct nvmm_assist_callbacks nvmm_callbacks = {
@@ -726,9 +727,9 @@
* Inner VCPU loop.
*/
do {
- if (cpu->vcpu_dirty) {
+ if (cpu->accel->dirty) {
nvmm_set_registers(cpu);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
if (qcpu->stop) {
@@ -826,32 +827,32 @@
do_nvmm_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
{
nvmm_get_registers(cpu);
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
}
static void
do_nvmm_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
{
nvmm_set_registers(cpu);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
static void
do_nvmm_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg)
{
nvmm_set_registers(cpu);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
static void
do_nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu, run_on_cpu_data arg)
{
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
}
void nvmm_cpu_synchronize_state(CPUState *cpu)
{
- if (!cpu->vcpu_dirty) {
+ if (!cpu->accel->dirty) {
run_on_cpu(cpu, do_nvmm_cpu_synchronize_state, RUN_ON_CPU_NULL);
}
}
@@ -981,7 +982,7 @@
}
}
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
cpu->accel = qcpu;
return 0;
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 4b965a5..ece22a3 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -21,6 +21,7 @@
#include <math.h>
#include "cpu.h"
#include "tcg-cpu.h"
+#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 31eec70..b08e644 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -237,6 +237,7 @@
uint64_t tpr;
uint64_t apic_base;
bool interruption_pending;
+ bool dirty;
/* Must be the last field as it may have a tail */
WHV_RUN_VP_EXIT_CONTEXT exit_ctx;
@@ -839,7 +840,7 @@
* The emulator just successfully wrote the register state. We clear the
* dirty state so we avoid the double write on resume of the VP.
*/
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
return hr;
}
@@ -1394,7 +1395,7 @@
/* Returns the address of the next instruction that is about to be executed. */
static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid)
{
- if (cpu->vcpu_dirty) {
+ if (cpu->accel->dirty) {
/* The CPU registers have been modified by other parts of QEMU. */
return cpu_env(cpu)->eip;
} else if (exit_context_valid) {
@@ -1713,9 +1714,9 @@
}
do {
- if (cpu->vcpu_dirty) {
+ if (cpu->accel->dirty) {
whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
if (exclusive_step_mode == WHPX_STEP_NONE) {
@@ -2063,9 +2064,9 @@
static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
{
- if (!cpu->vcpu_dirty) {
+ if (!cpu->accel->dirty) {
whpx_get_registers(cpu);
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
}
}
@@ -2073,20 +2074,20 @@
run_on_cpu_data arg)
{
whpx_set_registers(cpu, WHPX_SET_RESET_STATE);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
static void do_whpx_cpu_synchronize_post_init(CPUState *cpu,
run_on_cpu_data arg)
{
whpx_set_registers(cpu, WHPX_SET_FULL_STATE);
- cpu->vcpu_dirty = false;
+ cpu->accel->dirty = false;
}
static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu,
run_on_cpu_data arg)
{
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
}
/*
@@ -2095,7 +2096,7 @@
void whpx_cpu_synchronize_state(CPUState *cpu)
{
- if (!cpu->vcpu_dirty) {
+ if (!cpu->accel->dirty) {
run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL);
}
}
@@ -2235,7 +2236,7 @@
}
vcpu->interruptable = true;
- cpu->vcpu_dirty = true;
+ cpu->accel->dirty = true;
cpu->accel = vcpu;
max_vcpu_index = max(max_vcpu_index, cpu->cpu_index);
qemu_add_vm_change_state_handler(whpx_cpu_update_state, env);
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index cfe195d..db5ad1c 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -14,4 +14,6 @@
#define TARGET_PAGE_BITS 12
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ec37579..abb01b2 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -39,8 +39,6 @@
#define IOCSR_MEM_SIZE 0x428
-#define TCG_GUEST_DEFAULT_MO (0)
-
#define FCSR0_M1 0x1f /* FCSR1 mask, Enables */
#define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */
#define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */
diff --git a/target/meson.build b/target/meson.build
index 59b46b2..1c2e6f2 100644
--- a/target/meson.build
+++ b/target/meson.build
@@ -18,5 +18,3 @@
subdir('sparc')
subdir('tricore')
subdir('xtensa')
-
-specific_ss.add(files('target-common.c'))
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index 9770b0e..e530fea 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -29,4 +29,7 @@
/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
#define TARGET_PAGE_BITS 12
+/* MicroBlaze is always in-order. */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f8dc317..9eb7374 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -28,6 +28,7 @@
#include "qemu/module.h"
#include "hw/qdev-properties.h"
#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
#include "exec/gdbstub.h"
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index c0c7574..3e5a3e5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -24,9 +24,6 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
-/* MicroBlaze is always in-order. */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
typedef struct CPUArchState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index fc451be..6d89c1a 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
#include "tcg/tcg-op.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 594c91a..6f6ac16 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -30,4 +30,6 @@
#define TARGET_PAGE_BITS_MIN 12
#endif
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7329226..3e906a1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -10,8 +10,6 @@
#include "hw/clock.h"
#include "mips-defs.h"
-#define TCG_GUEST_DEFAULT_MO (0)
-
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
/* MSA Context */
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 3f08207..fbfc0f5 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -13,4 +13,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b1b7db5..c9fe9ae 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -24,8 +24,6 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
-#define TCG_GUEST_DEFAULT_MO (0)
-
/**
* OpenRISCCPUClass:
* @parent_realize: The parent class' realize handler.
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index b7ad52d..77c5ed9 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -40,4 +40,6 @@
# define TARGET_PAGE_BITS 12
#endif
+#define TCG_GUEST_DEFAULT_MO 0
+
#endif
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 67e6b2e..0ac55d6 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -29,8 +29,6 @@
#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
-#define TCG_GUEST_DEFAULT_MO 0
-
#define TARGET_PAGE_BITS_64K 16
#define TARGET_PAGE_BITS_16M 24
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 674c05a..0712098 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -142,7 +142,7 @@
return !!(env->msr & ((target_ulong)1 << MSR_LE));
}
-static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr)
+static uint32_t ppc_ldl_code(CPUArchState *env, target_ulong addr)
{
uint32_t insn = cpu_ldl_code(env, addr);
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 5b20ecb..601c0b5 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -18,6 +18,7 @@
#ifndef PPC_INTERNAL_H
#define PPC_INTERNAL_H
+#include "exec/breakpoint.h"
#include "hw/registerfields.h"
/* PM instructions */
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index b2a9396..1fbd649 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -28,4 +28,6 @@
* - M mode HLV/HLVX/HSV 0b111
*/
+#define TCG_GUEST_DEFAULT_MO 0
+
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3b1a02b..2d0c02c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -43,8 +43,6 @@
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
-#define TCG_GUEST_DEFAULT_MO 0
-
/*
* RISC-V-specific extra insn start words:
* 1: Original instruction opcode
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index 5794aa6..c347863 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -22,6 +22,8 @@
#ifndef RISCV_DEBUG_H
#define RISCV_DEBUG_H
+#include "exec/breakpoint.h"
+
#define RV_MAX_TRIGGERS 2
/* register index of tdata CSRs */
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index 84ca086..11d23b6 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -13,4 +13,10 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
+/*
+ * The z/Architecture has a strong memory model with some
+ * store-after-load re-ordering.
+ */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
#endif
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 43a46a5..414680e 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -33,9 +33,6 @@
#define ELF_MACHINE_UNAME "S390X"
-/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
#define TARGET_HAS_PRECISE_SMC
#define TARGET_INSN_START_EXTRA_WORDS 2
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index cb11980..82293fb 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -23,4 +23,27 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+/*
+ * From Oracle SPARC Architecture 2015:
+ *
+ * Compatibility notes: The PSO memory model described in SPARC V8 and
+ * SPARC V9 compatibility architecture specifications was never implemented
+ * in a SPARC V9 implementation and is not included in the Oracle SPARC
+ * Architecture specification.
+ *
+ * The RMO memory model described in the SPARC V9 specification was
+ * implemented in some non-Sun SPARC V9 implementations, but is not
+ * directly supported in Oracle SPARC Architecture 2015 implementations.
+ *
+ * Therefore always use TSO in QEMU.
+ *
+ * D.5 Specification of Partial Store Order (PSO)
+ * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
+ *
+ * D.6 Specification of Total Store Order (TSO)
+ * ... PSO with the additional requirement that all [stores] are followed
+ * by an implied MEMBAR #StoreStore.
+ */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
+
#endif
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index f3cdd17..dfd9512 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -6,29 +6,6 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
-/*
- * From Oracle SPARC Architecture 2015:
- *
- * Compatibility notes: The PSO memory model described in SPARC V8 and
- * SPARC V9 compatibility architecture specifications was never implemented
- * in a SPARC V9 implementation and is not included in the Oracle SPARC
- * Architecture specification.
- *
- * The RMO memory model described in the SPARC V9 specification was
- * implemented in some non-Sun SPARC V9 implementations, but is not
- * directly supported in Oracle SPARC Architecture 2015 implementations.
- *
- * Therefore always use TSO in QEMU.
- *
- * D.5 Specification of Partial Store Order (PSO)
- * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
- *
- * D.6 Specification of Total Store Order (TSO)
- * ... PSO with the additional requirement that all [stores] are followed
- * by an implied MEMBAR #StoreStore.
- */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
-
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
#define TARGET_FCCREGS 1
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
index 07ea81a..ec0036e 100644
--- a/target/sparc/gdbstub.c
+++ b/target/sparc/gdbstub.c
@@ -108,7 +108,7 @@
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
#if defined(TARGET_ABI32)
- abi_ulong tmp;
+ uint32_t tmp;
tmp = ldl_p(mem_buf);
#else
diff --git a/target/target-common.c b/target/target-common.c
deleted file mode 100644
index 903b10c..0000000
--- a/target/target-common.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-#include "qemu/osdep.h"
-
-#include "cpu.h"
-#include "exec/target_page.h"
-
-int qemu_target_page_mask(void)
-{
- return TARGET_PAGE_MASK;
-}
diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c
index f9309c5..29a7005 100644
--- a/target/tricore/gdbstub.c
+++ b/target/tricore/gdbstub.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "gdbstub/helpers.h"
+#include "cpu.h"
#define LCX_REGNUM 32
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index b1da055..0000725 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -17,4 +17,7 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+/* Xtensa processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
+
#endif
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 6b8d063..9f2341d 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -34,9 +34,6 @@
#include "hw/clock.h"
#include "xtensa-isa.h"
-/* Xtensa processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
enum {
/* Additional instructions */
XTENSA_OPTION_CODE_DENSITY,
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 0c0bb9d..6a32656 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -57,7 +57,7 @@
#include "tcg-internal.h"
#include "tcg/perf.h"
#ifdef CONFIG_USER_ONLY
-#include "exec/user/guest-base.h"
+#include "user/guest-base.h"
#endif
/* Forward declarations for functions declared in tcg-target.c.inc and
