)]}'
{
  "commit": "fca2817fdcb00e65020c2dcfcb0b23b2a20ea3c4",
  "tree": "534c1788a5de453e84ff6d1e660e64b20665b756",
  "parents": [
    "8001d22b0c67b2fbf8f2cb7b2f44bd7b46b360c1"
  ],
  "author": {
    "name": "Richard Henderson",
    "email": "richard.henderson@linaro.org",
    "time": "Fri Mar 28 12:55:24 2025 -0500"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Mon Mar 31 21:32:43 2025 +0200"
  },
  "message": "target/mips: Revert TARGET_PAGE_BITS_VARY\n\nRevert ee3863b9d41 and a08d60bc6c2b.  The logic behind changing\nthe system page size because of what the Loongson kernel \"prefers\"\nis flawed.\n\nIn the Loongson-2E manual, section 5.5, it is clear that the cpu\nsupports a 4k page size (along with many others).  Similarly for\nthe Loongson-3 series CPUs, the 4k page size is mentioned in the\nsection 7.7 (PageMask Register).  Therefore we must continue to\nsupport a 4k page size.\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-ID: \u003c20250328175526.368121-2-richard.henderson@linaro.org\u003e\n[PMD: Mention Loongson-3 series CPUs]\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "646044e274976280b65cb0e56441464d9ef8ff64",
      "old_mode": 33188,
      "old_path": "hw/mips/fuloong2e.c",
      "new_id": "2a8507b8b0a883962865d9bee06962250f2381f6",
      "new_mode": 33188,
      "new_path": "hw/mips/fuloong2e.c"
    },
    {
      "type": "modify",
      "old_id": "db1cc5131471ae915f0373642a0191acc7eb8095",
      "old_mode": 33188,
      "old_path": "hw/mips/loongson3_virt.c",
      "new_id": "1da20dccec4f159fd58672502d113e406b7a9916",
      "new_mode": 33188,
      "new_path": "hw/mips/loongson3_virt.c"
    },
    {
      "type": "modify",
      "old_id": "11b3ac0ac630cfa4ec2346d8ff153daf6dfc6125",
      "old_mode": 33188,
      "old_path": "target/mips/cpu-param.h",
      "new_id": "8fcb1b4f5f2c79b585b42570fc758716b9c00809",
      "new_mode": 33188,
      "new_path": "target/mips/cpu-param.h"
    },
    {
      "type": "modify",
      "old_id": "01a07a169f6de35c4d7942678ef81adec43a50f0",
      "old_mode": 33188,
      "old_path": "target/mips/tcg/system/cp0_helper.c",
      "new_id": "8c2114c58a61e984afde73709c125f29d9905b31",
      "new_mode": 33188,
      "new_path": "target/mips/tcg/system/cp0_helper.c"
    },
    {
      "type": "modify",
      "old_id": "ca4d6b27bc94e8b09bccdf9a9cf120f230bfa763",
      "old_mode": 33188,
      "old_path": "target/mips/tcg/system/tlb_helper.c",
      "new_id": "123639fa18ea7b282062b1e38ae2f04d1ff7554d",
      "new_mode": 33188,
      "new_path": "target/mips/tcg/system/tlb_helper.c"
    }
  ]
}