)]}'
{
  "commit": "fc976a67ded4232cf0b9ae3c11fe051da01e4456",
  "tree": "4de2eca6f62b50d90159900bdb0717763e0a7526",
  "parents": [
    "dacfec5157fb9e2249cf393a143bd545e80a6e31"
  ],
  "author": {
    "name": "Ilya Leoshkevich",
    "email": "iii@linux.ibm.com",
    "time": "Thu Oct 16 19:58:32 2025 +0200"
  },
  "committer": {
    "name": "Thomas Huth",
    "email": "thuth@redhat.com",
    "time": "Mon Nov 03 08:27:59 2025 +0100"
  },
  "message": "target/s390x: Use address generation for register branch targets\n\nIndirect branches to addresses taken from registers go through address\ngeneration, e.g., for BRANCH ON CONDITION Principles of Operation says:\n\n    In the RR format, the contents of general register R2 are used to\n    generate the branch address\n\nQEMU uses r2_nz handler for the respective register operands. Currently\nit does not zero out extra bits in 24- and 31-bit addressing modes as\nrequired by address generation. The very frequently used\ns390x_tr_init_disas_context() function has a workaround for this,\nbut the code for saving an old PSW during an interrupt does not.\n\nAdd the missing masking to r2_nz. Enforce PSW validity by replacing the\nworkaround with an assertion.\n\nReported-by: Thomas Weißschuh \u003clinux@weissschuh.net\u003e\nReported-by: Heiko Carstens \u003chca@linux.ibm.com\u003e\nLink: https://lore.kernel.org/lkml/ab3131a2-c42a-47ff-bf03-e9f68ac053c0@t-8ch.de/\nCc: qemu-stable@nongnu.org\nSigned-off-by: Ilya Leoshkevich \u003ciii@linux.ibm.com\u003e\nTested-by: Thomas Weißschuh \u003clinux@weissschuh.net\u003e\nMessage-ID: \u003c20251016175954.41153-4-iii@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ec9e5a07516af3dd275481d8ab3d3c358d823af9",
      "old_mode": 33188,
      "old_path": "target/s390x/tcg/translate.c",
      "new_id": "4d2b8c5e2be7f720c9c2113daec7e66dcef744b8",
      "new_mode": 33188,
      "new_path": "target/s390x/tcg/translate.c"
    }
  ]
}