commit fc63010e9bb9efa95221f2873edb2006a40d4b6c
author Philippe Mathieu-Daudé <f4bug@amsat.org> Sun Jan 10 22:44:59 2021 +0100
committer Philippe Mathieu-Daudé <f4bug@amsat.org> Thu Jan 14 17:13:54 2021 +0100
tree 769b0e12d9ba6b615b82589d578186b82d1a745c
parent 6648042afb23ad01866af821b5053351a6196ea3

target/mips: Remove CPU_NANOMIPS32 definition

nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>

target/mips/cpu-defs.c.inc

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index ba22ff4..9f7bac8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -486,8 +486,8 @@
         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
         .SEGBITS = 32,
         .PABITS = 32,
-        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
-                      ASE_MT,
+        .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
+                      ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
         .mmu_type = MMU_TYPE_R4000,
     },
 #if defined(TARGET_MIPS64)

target/mips/mips-defs.h

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b7879be..3704db8 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -86,9 +86,6 @@
 #define CPU_MIPS32R6    (CPU_MIPS32R5 | ISA_MIPS_R6)
 #define CPU_MIPS64R6    (CPU_MIPS64R5 | CPU_MIPS32R6)
 
-/* Wave Computing: "nanoMIPS" */
-#define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)
-
 #define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
 
 /*