commit fb6bbafc0f19385fb257ee073ed13dcaf613f2f8
author Tom Lendacky <thomas.lendacky@amd.com> Fri Sep 30 10:14:30 2022 -0500
committer Paolo Bonzini <pbonzini@redhat.com> Fri Apr 28 12:50:34 2023 +0200
tree adbd085044cb70a582e41400aa5aee76b214c314
parent 8168fed9f84e3128f7628969ae78af49433d5ce7

i386/cpu: Update how the EBX register of CPUID 0x8000001F is set

Update the setting of CPUID 0x8000001F EBX to clearly document the ranges
associated with fields being set.

Fixes: 6cb8f2a663 ("cpu/i386: populate CPUID 0x8000_001F when SEV is active")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <5822fd7d02b575121380e1f493a8f6d9eba2b11a.1664550870.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

target/i386/cpu.c

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2e30e34..73dd993 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6000,8 +6000,8 @@
         if (sev_enabled()) {
             *eax = 0x2;
             *eax |= sev_es_enabled() ? 0x8 : 0;
-            *ebx = sev_get_cbit_position();
-            *ebx |= sev_get_reduced_phys_bits() << 6;
+            *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
+            *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
         }
         break;
     default: