)]}'
{
  "commit": "faacd2e6b6a85a5eee2472e5a7f50bf69c4ad44a",
  "tree": "acc88c8134f1a2aaebab4aae34af268c1a0dc2ac",
  "parents": [
    "a54dd0cd6b9119c44d52547f51a529122f0ec1f1"
  ],
  "author": {
    "name": "Sunil V L",
    "email": "sunilvl@ventanamicro.com",
    "time": "Tue Jul 16 20:12:59 2024 +0530"
  },
  "committer": {
    "name": "Michael S. Tsirkin",
    "email": "mst@redhat.com",
    "time": "Mon Jul 22 20:15:42 2024 -0400"
  },
  "message": "hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART\n\nThe requirement ACPI_060 in the RISC-V BRS specification [1], requires\nNS16550 compatible UART to have the HID RSCV0003. So, update the HID for\nthe UART.\n\n[1] -  https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf\n       (Chapter 6)\n\nSigned-off-by: Sunil V L \u003csunilvl@ventanamicro.com\u003e\nAcked-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nReviewed-by: Igor Mammedov \u003cimammedo@redhat.com\u003e\nMessage-Id: \u003c20240716144306.2432257-3-sunilvl@ventanamicro.com\u003e\nReviewed-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5f5082a35bb0a573595f54579f873216546bb2a7",
      "old_mode": 33188,
      "old_path": "hw/riscv/virt-acpi-build.c",
      "new_id": "36d6a3a412f11f57378c022a06691a7715e591e8",
      "new_mode": 33188,
      "new_path": "hw/riscv/virt-acpi-build.c"
    }
  ]
}