Merge tag 'pull-loongarch-20230526' of https://gitlab.com/gaosong/qemu into staging
pull-loongarch-20230526
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* tag 'pull-loongarch-20230526' of https://gitlab.com/gaosong/qemu:
target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump
target/loongarch: Fix LD/ST{LE/GT} instructions get wrong CSR_ERA and CSR_BADV
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index c0afc21..ad93eca 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -187,10 +187,10 @@
case EXCCODE_IPE:
case EXCCODE_FPD:
case EXCCODE_FPE:
- case EXCCODE_BCE:
case EXCCODE_SXD:
env->CSR_BADV = env->pc;
QEMU_FALLTHROUGH;
+ case EXCCODE_BCE:
case EXCCODE_ADEM:
case EXCCODE_PIL:
case EXCCODE_PIS:
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
index 0be2b5a..68779da 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -3963,106 +3963,119 @@
static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st8_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st8_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm)));
return true;
}
static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st16_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st16_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm)));
return true;
}
static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st32_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st32_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)));
return true;
}
static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm)));
return true;
}
static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld8s_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld8s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}
static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld16s_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld16s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}
static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld32s_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld32s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}
static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}
static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld8u_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld8u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}
static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld16u_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld16u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}
static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld32u_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld32u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}
static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}
static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
- 16, ctx->vl/8, cpu_gpr[a->rj]);
+ 16, ctx->vl/8, src);
return true;
}
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index 568c071..60335a05 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -49,14 +49,16 @@
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj > rk) {
- do_raise_exception(env, EXCCODE_BCE, 0);
+ env->CSR_BADV = rj;
+ do_raise_exception(env, EXCCODE_BCE, GETPC());
}
}
void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj <= rk) {
- do_raise_exception(env, EXCCODE_BCE, 0);
+ env->CSR_BADV = rj;
+ do_raise_exception(env, EXCCODE_BCE, GETPC());
}
}
