Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* move Coverity builds to Gitlab CI
* fix two memory leaks
* bug fixes
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Mar 2024 18:11:15 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
gitlab-ci: add manual job to run Coverity
run-coverity-scan: add --check-upload-only option
mips: do not list individual devices from configs/
oslib-posix: fix memory leak in touch_all_pages
hw/intc/apic: fix memory leak
hw/scsi/lsi53c895a: stop script on phase mismatch
meson: Remove --warn-common ldflag
system/qdev-monitor: move drain_call_rcu call under if (!dev) in qmp_device_add()
hw/scsi/lsi53c895a: add timer to scripts processing
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 4183f2f..4d96f85 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1133,6 +1133,7 @@
F: hw/misc/stm32l4x5_exti.c
F: hw/misc/stm32l4x5_syscfg.c
F: hw/misc/stm32l4x5_rcc.c
+F: hw/gpio/stm32l4x5_gpio.c
F: include/hw/*/stm32l4x5_*.h
B-L475E-IOT01A IoT Node
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
index b857a56..0afef8e 100644
--- a/docs/system/arm/b-l475e-iot01a.rst
+++ b/docs/system/arm/b-l475e-iot01a.rst
@@ -18,6 +18,7 @@
- STM32L4x5 EXTI (Extended interrupts and events controller)
- STM32L4x5 SYSCFG (System configuration controller)
- STM32L4x5 RCC (Reset and clock control)
+- STM32L4x5 GPIOs (General-purpose I/Os)
Missing devices
"""""""""""""""
@@ -25,7 +26,6 @@
The B-L475E-IOT01A does *not* support the following devices:
- Serial ports (UART)
-- General-purpose I/Os (GPIO)
- Analog to Digital Converter (ADC)
- SPI controller
- Timer controller (TIMER)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index f67aea2..2a7bbb8 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -28,6 +28,7 @@
- FEAT_DotProd (Advanced SIMD dot product instructions)
- FEAT_DoubleFault (Double Fault Extension)
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
+- FEAT_ECV (Enhanced Counter Virtualization)
- FEAT_EPAC (Enhanced pointer authentication)
- FEAT_ETS (Enhanced Translation Synchronization)
- FEAT_EVT (Enhanced Virtualization Traps)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index af66bde..6d4517c 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1994,6 +1994,59 @@
}
}
+void build_spcr(GArray *table_data, BIOSLinker *linker,
+ const AcpiSpcrData *f, const uint8_t rev,
+ const char *oem_id, const char *oem_table_id)
+{
+ AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
+ .oem_table_id = oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+ /* Interface type */
+ build_append_int_noprefix(table_data, f->interface_type, 1);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 3);
+ /* Base Address */
+ build_append_gas(table_data, f->base_addr.id, f->base_addr.width,
+ f->base_addr.offset, f->base_addr.size,
+ f->base_addr.addr);
+ /* Interrupt type */
+ build_append_int_noprefix(table_data, f->interrupt_type, 1);
+ /* IRQ */
+ build_append_int_noprefix(table_data, f->pc_interrupt, 1);
+ /* Global System Interrupt */
+ build_append_int_noprefix(table_data, f->interrupt, 4);
+ /* Baud Rate */
+ build_append_int_noprefix(table_data, f->baud_rate, 1);
+ /* Parity */
+ build_append_int_noprefix(table_data, f->parity, 1);
+ /* Stop Bits */
+ build_append_int_noprefix(table_data, f->stop_bits, 1);
+ /* Flow Control */
+ build_append_int_noprefix(table_data, f->flow_control, 1);
+ /* Language */
+ build_append_int_noprefix(table_data, f->language, 1);
+ /* Terminal Type */
+ build_append_int_noprefix(table_data, f->terminal_type, 1);
+ /* PCI Device ID */
+ build_append_int_noprefix(table_data, f->pci_device_id, 2);
+ /* PCI Vendor ID */
+ build_append_int_noprefix(table_data, f->pci_vendor_id, 2);
+ /* PCI Bus Number */
+ build_append_int_noprefix(table_data, f->pci_bus, 1);
+ /* PCI Device Number */
+ build_append_int_noprefix(table_data, f->pci_device, 1);
+ /* PCI Function Number */
+ build_append_int_noprefix(table_data, f->pci_function, 1);
+ /* PCI Flags */
+ build_append_int_noprefix(table_data, f->pci_flags, 4);
+ /* PCI Segment */
+ build_append_int_noprefix(table_data, f->pci_segment, 1);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+
+ acpi_table_end(linker, &table);
+}
/*
* ACPI spec, Revision 6.3
* 5.2.29 Processor Properties Topology Table (PPTT)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index d58d820..893a7bf 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -473,9 +473,10 @@
bool
select ARM_V7M
select OR_IRQ
- select STM32L4X5_SYSCFG
select STM32L4X5_EXTI
+ select STM32L4X5_SYSCFG
select STM32L4X5_RCC
+ select STM32L4X5_GPIO
config XLNX_ZYNQMP_ARM
bool
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index bf99260..40e294f 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -28,6 +28,7 @@
#include "sysemu/sysemu.h"
#include "hw/or-irq.h"
#include "hw/arm/stm32l4x5_soc.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
@@ -99,6 +100,22 @@
16, 35, 36, 37, 38,
};
+static const struct {
+ uint32_t addr;
+ uint32_t moder_reset;
+ uint32_t ospeedr_reset;
+ uint32_t pupdr_reset;
+} stm32l4x5_gpio_cfg[NUM_GPIOS] = {
+ { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
+ { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
+ { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
+ { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
+ { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
+ { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
+ { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
+ { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
+};
+
static void stm32l4x5_soc_initfn(Object *obj)
{
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
@@ -110,6 +127,11 @@
}
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
+
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
+ g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
+ }
}
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -118,8 +140,9 @@
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
MemoryRegion *system_memory = get_system_memory();
- DeviceState *armv7m;
+ DeviceState *armv7m, *dev;
SysBusDevice *busdev;
+ uint32_t pin_index;
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
sc->flash_size, errp)) {
@@ -160,17 +183,43 @@
return;
}
+ /* GPIOs */
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
+ g_autofree char *name = g_strdup_printf("%c", 'A' + i);
+ dev = DEVICE(&s->gpio[i]);
+ qdev_prop_set_string(dev, "name", name);
+ qdev_prop_set_uint32(dev, "mode-reset",
+ stm32l4x5_gpio_cfg[i].moder_reset);
+ qdev_prop_set_uint32(dev, "ospeed-reset",
+ stm32l4x5_gpio_cfg[i].ospeedr_reset);
+ qdev_prop_set_uint32(dev, "pupd-reset",
+ stm32l4x5_gpio_cfg[i].pupdr_reset);
+ busdev = SYS_BUS_DEVICE(&s->gpio[i]);
+ g_free(name);
+ name = g_strdup_printf("gpio%c-out", 'a' + i);
+ qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
+ if (!sysbus_realize(busdev, errp)) {
+ return;
+ }
+ sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);
+ }
+
/* System configuration controller */
busdev = SYS_BUS_DEVICE(&s->syscfg);
if (!sysbus_realize(busdev, errp)) {
return;
}
sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
- /*
- * TODO: when the GPIO device is implemented, connect it
- * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
- * GPIO_NUM_PINS.
- */
+
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
+ for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {
+ pin_index = GPIO_NUM_PINS * i + j;
+ qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,
+ qdev_get_gpio_in(DEVICE(&s->syscfg),
+ pin_index));
+ }
+ }
/* EXTI device */
busdev = SYS_BUS_DEVICE(&s->exti);
@@ -217,7 +266,7 @@
}
}
- for (unsigned i = 0; i < 16; i++) {
+ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
qdev_get_gpio_in(DEVICE(&s->exti), i));
}
@@ -302,14 +351,6 @@
/* RESERVED: 0x40024400, 0x7FDBC00 */
/* AHB2 BUS */
- create_unimplemented_device("GPIOA", 0x48000000, 0x400);
- create_unimplemented_device("GPIOB", 0x48000400, 0x400);
- create_unimplemented_device("GPIOC", 0x48000800, 0x400);
- create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
- create_unimplemented_device("GPIOE", 0x48001000, 0x400);
- create_unimplemented_device("GPIOF", 0x48001400, 0x400);
- create_unimplemented_device("GPIOG", 0x48001800, 0x400);
- create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
/* RESERVED: 0x48002000, 0x7FDBC00 */
create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
create_unimplemented_device("ADC", 0x50040000, 0x400);
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 8414122..6a1bde6 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -431,48 +431,34 @@
* Rev: 1.07
*/
static void
-build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
- .oem_table_id = vms->oem_table_id };
+ AcpiSpcrData serial = {
+ .interface_type = 3, /* ARM PL011 UART */
+ .base_addr.id = AML_AS_SYSTEM_MEMORY,
+ .base_addr.width = 32,
+ .base_addr.offset = 0,
+ .base_addr.size = 3,
+ .base_addr.addr = vms->memmap[VIRT_UART].base,
+ .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/
+ .pc_interrupt = 0, /* IRQ */
+ .interrupt = (vms->irqmap[VIRT_UART] + ARM_SPI_BASE),
+ .baud_rate = 3, /* 9600 */
+ .parity = 0, /* No Parity */
+ .stop_bits = 1, /* 1 Stop bit */
+ .flow_control = 1 << 1, /* RTS/CTS hardware flow control */
+ .terminal_type = 0, /* VT100 */
+ .language = 0, /* Language */
+ .pci_device_id = 0xffff, /* not a PCI device*/
+ .pci_vendor_id = 0xffff, /* not a PCI device*/
+ .pci_bus = 0,
+ .pci_device = 0,
+ .pci_function = 0,
+ .pci_flags = 0,
+ .pci_segment = 0,
+ };
- acpi_table_begin(&table, table_data);
-
- /* Interface Type */
- build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
- build_append_int_noprefix(table_data, 0, 3); /* Reserved */
- /* Base Address */
- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
- vms->memmap[VIRT_UART].base);
- /* Interrupt Type */
- build_append_int_noprefix(table_data,
- (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
- build_append_int_noprefix(table_data, 0, 1); /* IRQ */
- /* Global System Interrupt */
- build_append_int_noprefix(table_data,
- vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
- build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */
- build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */
- /* Stop Bits */
- build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1);
- /* Flow Control */
- build_append_int_noprefix(table_data,
- (1 << 1) /* RTS/CTS hardware flow control */, 1);
- /* Terminal Type */
- build_append_int_noprefix(table_data, 0 /* VT100 */, 1);
- build_append_int_noprefix(table_data, 0, 1); /* Language */
- /* PCI Device ID */
- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
- /* PCI Vendor ID */
- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
- build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */
- build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */
- build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */
- build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */
- build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */
- build_append_int_noprefix(table_data, 0, 4); /* Reserved */
-
- acpi_table_end(linker, &table);
+ build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
}
/*
@@ -938,7 +924,7 @@
}
acpi_add_table(table_offsets, tables_blob);
- build_spcr(tables_blob, tables->linker, vms);
+ spcr_setup(tables_blob, tables->linker, vms);
acpi_add_table(table_offsets, tables_blob);
build_dbg2(tables_blob, tables->linker, vms);
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index d2cf3ac..712940b 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -16,3 +16,6 @@
config SIFIVE_GPIO
bool
+
+config STM32L4X5_GPIO
+ bool
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 8a8d03d..3454b50 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -13,5 +13,6 @@
'bcm2835_gpio.c',
'bcm2838_gpio.c'
))
+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c
new file mode 100644
index 0000000..63b8763
--- /dev/null
+++ b/hw/gpio/stm32l4x5_gpio.c
@@ -0,0 +1,477 @@
+/*
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
+ *
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
+#include "hw/irq.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "qapi/visitor.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+#define GPIO_MODER 0x00
+#define GPIO_OTYPER 0x04
+#define GPIO_OSPEEDR 0x08
+#define GPIO_PUPDR 0x0C
+#define GPIO_IDR 0x10
+#define GPIO_ODR 0x14
+#define GPIO_BSRR 0x18
+#define GPIO_LCKR 0x1C
+#define GPIO_AFRL 0x20
+#define GPIO_AFRH 0x24
+#define GPIO_BRR 0x28
+#define GPIO_ASCR 0x2C
+
+/* 0b11111111_11111111_00000000_00000000 */
+#define RESERVED_BITS_MASK 0xFFFF0000
+
+static void update_gpio_idr(Stm32l4x5GpioState *s);
+
+static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
+{
+ return extract32(s->pupdr, 2 * pin, 2) == 1;
+}
+
+static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
+{
+ return extract32(s->pupdr, 2 * pin, 2) == 2;
+}
+
+static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
+{
+ return extract32(s->moder, 2 * pin, 2) == 1;
+}
+
+static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
+{
+ return extract32(s->otyper, pin, 1) == 1;
+}
+
+static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
+{
+ return extract32(s->otyper, pin, 1) == 0;
+}
+
+static void stm32l4x5_gpio_reset_hold(Object *obj)
+{
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
+
+ s->moder = s->moder_reset;
+ s->otyper = 0x00000000;
+ s->ospeedr = s->ospeedr_reset;
+ s->pupdr = s->pupdr_reset;
+ s->idr = 0x00000000;
+ s->odr = 0x00000000;
+ s->lckr = 0x00000000;
+ s->afrl = 0x00000000;
+ s->afrh = 0x00000000;
+ s->ascr = 0x00000000;
+
+ s->disconnected_pins = 0xFFFF;
+ s->pins_connected_high = 0x0000;
+ update_gpio_idr(s);
+}
+
+static void stm32l4x5_gpio_set(void *opaque, int line, int level)
+{
+ Stm32l4x5GpioState *s = opaque;
+ /*
+ * The pin isn't set if line is configured in output mode
+ * except if level is 0 and the output is open-drain.
+ * This way there will be no short-circuit prone situations.
+ */
+ if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
+ line);
+ return;
+ }
+
+ s->disconnected_pins &= ~(1 << line);
+ if (level) {
+ s->pins_connected_high |= (1 << line);
+ } else {
+ s->pins_connected_high &= ~(1 << line);
+ }
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
+ s->pins_connected_high);
+ update_gpio_idr(s);
+}
+
+
+static void update_gpio_idr(Stm32l4x5GpioState *s)
+{
+ uint32_t new_idr_mask = 0;
+ uint32_t new_idr = s->odr;
+ uint32_t old_idr = s->idr;
+ int new_pin_state, old_pin_state;
+
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
+ if (is_output(s, i)) {
+ if (is_push_pull(s, i)) {
+ new_idr_mask |= (1 << i);
+ } else if (!(s->odr & (1 << i))) {
+ /* open-drain ODR 0 */
+ new_idr_mask |= (1 << i);
+ /* open-drain ODR 1 */
+ } else if (!(s->disconnected_pins & (1 << i)) &&
+ !(s->pins_connected_high & (1 << i))) {
+ /* open-drain ODR 1 with pin connected low */
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ /* open-drain ODR 1 with unactive pin */
+ } else if (is_pull_up(s, i)) {
+ new_idr_mask |= (1 << i);
+ } else if (is_pull_down(s, i)) {
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ }
+ /*
+ * The only case left is for open-drain ODR 1
+ * with unactive pin without pull-up or pull-down :
+ * the value is floating.
+ */
+ /* input or analog mode with connected pin */
+ } else if (!(s->disconnected_pins & (1 << i))) {
+ if (s->pins_connected_high & (1 << i)) {
+ /* pin high */
+ new_idr_mask |= (1 << i);
+ new_idr |= (1 << i);
+ } else {
+ /* pin low */
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ }
+ /* input or analog mode with disconnected pin */
+ } else {
+ if (is_pull_up(s, i)) {
+ /* pull-up */
+ new_idr_mask |= (1 << i);
+ new_idr |= (1 << i);
+ } else if (is_pull_down(s, i)) {
+ /* pull-down */
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ }
+ /*
+ * The only case left is for a disconnected pin
+ * without pull-up or pull-down :
+ * the value is floating.
+ */
+ }
+ }
+
+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
+ trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
+
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
+ if (new_idr_mask & (1 << i)) {
+ new_pin_state = (new_idr & (1 << i)) > 0;
+ old_pin_state = (old_idr & (1 << i)) > 0;
+ if (new_pin_state > old_pin_state) {
+ qemu_irq_raise(s->pin[i]);
+ } else if (new_pin_state < old_pin_state) {
+ qemu_irq_lower(s->pin[i]);
+ }
+ }
+ }
+}
+
+/*
+ * Return mask of pins that are both configured in output
+ * mode and externally driven (except pins in open-drain
+ * mode externally set to 0).
+ */
+static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
+{
+ uint32_t pins_to_disconnect = 0;
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
+ /* for each connected pin in output mode */
+ if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
+ /* if either push-pull or high level */
+ if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
+ pins_to_disconnect |= (1 << i);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Line %d can't be driven externally\n",
+ i);
+ }
+ }
+ }
+ return pins_to_disconnect;
+}
+
+/*
+ * Set field `disconnected_pins` and call `update_gpio_idr()`
+ */
+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
+{
+ s->disconnected_pins |= lines;
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
+ s->pins_connected_high);
+ update_gpio_idr(s);
+}
+
+static void disconnected_pins_set(Object *obj, Visitor *v,
+ const char *name, void *opaque, Error **errp)
+{
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
+ uint16_t value;
+ if (!visit_type_uint16(v, name, &value, errp)) {
+ return;
+ }
+ disconnect_gpio_pins(s, value);
+}
+
+static void disconnected_pins_get(Object *obj, Visitor *v,
+ const char *name, void *opaque, Error **errp)
+{
+ visit_type_uint16(v, name, (uint16_t *)opaque, errp);
+}
+
+static void clock_freq_get(Object *obj, Visitor *v,
+ const char *name, void *opaque, Error **errp)
+{
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
+ uint32_t clock_freq_hz = clock_get_hz(s->clk);
+ visit_type_uint32(v, name, &clock_freq_hz, errp);
+}
+
+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ Stm32l4x5GpioState *s = opaque;
+
+ uint32_t value = val64;
+ trace_stm32l4x5_gpio_write(s->name, addr, val64);
+
+ switch (addr) {
+ case GPIO_MODER:
+ s->moder = value;
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Analog and AF modes aren't supported\n\
+ Analog and AF mode behave like input mode\n",
+ __func__);
+ return;
+ case GPIO_OTYPER:
+ s->otyper = value & ~RESERVED_BITS_MASK;
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
+ return;
+ case GPIO_OSPEEDR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Changing I/O output speed isn't supported\n\
+ I/O speed is already maximal\n",
+ __func__);
+ s->ospeedr = value;
+ return;
+ case GPIO_PUPDR:
+ s->pupdr = value;
+ update_gpio_idr(s);
+ return;
+ case GPIO_IDR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: GPIO->IDR is read-only\n",
+ __func__);
+ return;
+ case GPIO_ODR:
+ s->odr = value & ~RESERVED_BITS_MASK;
+ update_gpio_idr(s);
+ return;
+ case GPIO_BSRR: {
+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
+ /* If both BSx and BRx are set, BSx has priority.*/
+ s->odr &= ~bits_to_reset;
+ s->odr |= bits_to_set;
+ update_gpio_idr(s);
+ return;
+ }
+ case GPIO_LCKR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Locking port bits configuration isn't supported\n",
+ __func__);
+ s->lckr = value & ~RESERVED_BITS_MASK;
+ return;
+ case GPIO_AFRL:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Alternate functions aren't supported\n",
+ __func__);
+ s->afrl = value;
+ return;
+ case GPIO_AFRH:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Alternate functions aren't supported\n",
+ __func__);
+ s->afrh = value;
+ return;
+ case GPIO_BRR: {
+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
+ s->odr &= ~bits_to_reset;
+ update_gpio_idr(s);
+ return;
+ }
+ case GPIO_ASCR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: ADC function isn't supported\n",
+ __func__);
+ s->ascr = value & ~RESERVED_BITS_MASK;
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+}
+
+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ Stm32l4x5GpioState *s = opaque;
+
+ trace_stm32l4x5_gpio_read(s->name, addr);
+
+ switch (addr) {
+ case GPIO_MODER:
+ return s->moder;
+ case GPIO_OTYPER:
+ return s->otyper;
+ case GPIO_OSPEEDR:
+ return s->ospeedr;
+ case GPIO_PUPDR:
+ return s->pupdr;
+ case GPIO_IDR:
+ return s->idr;
+ case GPIO_ODR:
+ return s->odr;
+ case GPIO_BSRR:
+ return 0;
+ case GPIO_LCKR:
+ return s->lckr;
+ case GPIO_AFRL:
+ return s->afrl;
+ case GPIO_AFRH:
+ return s->afrh;
+ case GPIO_BRR:
+ return 0;
+ case GPIO_ASCR:
+ return s->ascr;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+ }
+}
+
+static const MemoryRegionOps stm32l4x5_gpio_ops = {
+ .read = stm32l4x5_gpio_read,
+ .write = stm32l4x5_gpio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void stm32l4x5_gpio_init(Object *obj)
+{
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
+
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
+ TYPE_STM32L4X5_GPIO, 0x400);
+
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
+
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
+
+ object_property_add(obj, "disconnected-pins", "uint16",
+ disconnected_pins_get, disconnected_pins_set,
+ NULL, &s->disconnected_pins);
+ object_property_add(obj, "clock-freq-hz", "uint32",
+ clock_freq_get, NULL, NULL, NULL);
+}
+
+static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
+{
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
+ if (!clock_has_source(s->clk)) {
+ error_setg(errp, "GPIO: clk input must be connected");
+ return;
+ }
+}
+
+static const VMStateDescription vmstate_stm32l4x5_gpio = {
+ .name = TYPE_STM32L4X5_GPIO,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]){
+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),
+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property stm32l4x5_gpio_properties[] = {
+ DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
+ DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
+ DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
+ DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ device_class_set_props(dc, stm32l4x5_gpio_properties);
+ dc->vmsd = &vmstate_stm32l4x5_gpio;
+ dc->realize = stm32l4x5_gpio_realize;
+ rc->phases.hold = stm32l4x5_gpio_reset_hold;
+}
+
+static const TypeInfo stm32l4x5_gpio_types[] = {
+ {
+ .name = TYPE_STM32L4X5_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Stm32l4x5GpioState),
+ .instance_init = stm32l4x5_gpio_init,
+ .class_init = stm32l4x5_gpio_class_init,
+ },
+};
+
+DEFINE_TYPES(stm32l4x5_gpio_types)
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index 9736b36..9331f42 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -31,3 +31,9 @@
# aspeed_gpio.c
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
+
+# stm32l4x5_gpio.c
+stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
+stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"
+stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
diff --git a/hw/hyperv/hv-balloon.c b/hw/hyperv/hv-balloon.c
index ade2833..3a9ef07 100644
--- a/hw/hyperv/hv-balloon.c
+++ b/hw/hyperv/hv-balloon.c
@@ -366,7 +366,7 @@
PageRangeTree dtree;
uint64_t *dctr;
bool our_range;
- struct dm_unballoon_request *ur;
+ g_autofree struct dm_unballoon_request *ur = NULL;
size_t ur_size = sizeof(*ur) + sizeof(ur->range_array[0]);
PageRange range;
bool bret;
@@ -388,8 +388,7 @@
assert(dtree.t);
assert(dctr);
- ur = alloca(ur_size);
- memset(ur, 0, ur_size);
+ ur = g_malloc0(ur_size);
ur->hdr.type = DM_UNBALLOON_REQUEST;
ur->hdr.size = ur_size;
ur->hdr.trans_id = balloon->trans_id;
@@ -514,8 +513,8 @@
static void hv_balloon_hot_add_rb_wait(HvBalloon *balloon, StateDesc *stdesc)
{
VMBusChannel *chan = hv_balloon_get_channel(balloon);
- struct dm_hot_add *ha;
- size_t ha_size = sizeof(*ha) + sizeof(ha->range);
+ struct dm_hot_add_with_region *ha;
+ size_t ha_size = sizeof(*ha);
assert(balloon->state == S_HOT_ADD_RB_WAIT);
@@ -531,8 +530,8 @@
PageRange *hot_add_range = &balloon->hot_add_range;
uint64_t *current_count = &balloon->ha_current_count;
VMBusChannel *chan = hv_balloon_get_channel(balloon);
- struct dm_hot_add *ha;
- size_t ha_size = sizeof(*ha) + sizeof(ha->range);
+ g_autofree struct dm_hot_add_with_region *ha = NULL;
+ size_t ha_size = sizeof(*ha);
union dm_mem_page_range *ha_region;
uint64_t align, chunk_max_size;
ssize_t ret;
@@ -560,9 +559,8 @@
*/
*current_count = MIN(hot_add_range->count, chunk_max_size);
- ha = alloca(ha_size);
- ha_region = &(&ha->range)[1];
- memset(ha, 0, ha_size);
+ ha = g_malloc0(ha_size);
+ ha_region = &ha->region;
ha->hdr.type = DM_MEM_HOT_ADD_REQUEST;
ha->hdr.size = ha_size;
ha->hdr.trans_id = balloon->trans_id;
diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c
index 6c4a18d..3ea54ba 100644
--- a/hw/hyperv/hyperv.c
+++ b/hw/hyperv/hyperv.c
@@ -951,3 +951,15 @@
return msg.u.query_options.options;
}
+
+static bool vmbus_recommended_features_enabled;
+
+bool hyperv_are_vmbus_recommended_features_enabled(void)
+{
+ return vmbus_recommended_features_enabled;
+}
+
+void hyperv_set_vmbus_recommended_features_enabled(void)
+{
+ vmbus_recommended_features_enabled = true;
+}
diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
index 380239a..f33afee 100644
--- a/hw/hyperv/vmbus.c
+++ b/hw/hyperv/vmbus.c
@@ -2631,6 +2631,12 @@
return;
}
+ if (!hyperv_are_vmbus_recommended_features_enabled()) {
+ warn_report("VMBus enabled without the recommended set of Hyper-V features: "
+ "hv-stimer, hv-vapic and hv-runtime. "
+ "Some Windows versions might not boot or enable the VMBus device");
+ }
+
bridge->bus = VMBUS(qbus_new(TYPE_VMBUS, dev, "vmbus"));
}
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index e98e258..6a7fbfa 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -162,7 +162,7 @@
static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
uint32_t word)
{
- uint32_t i, irq, ret = 0;
+ uint32_t i, irq, sourcecfg, sm, raw_input, irq_inverted, ret = 0;
for (i = 0; i < 32; i++) {
irq = word * 32 + i;
@@ -170,7 +170,20 @@
continue;
}
- ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i;
+ sourcecfg = aplic->sourcecfg[irq];
+ if (sourcecfg & APLIC_SOURCECFG_D) {
+ continue;
+ }
+
+ sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+ continue;
+ }
+
+ raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0;
+ irq_inverted = (sm == APLIC_SOURCECFG_SM_LEVEL_LOW ||
+ sm == APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0;
+ ret |= (raw_input ^ irq_inverted) << i;
}
return ret;
@@ -218,13 +231,25 @@
}
sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
- if ((sm == APLIC_SOURCECFG_SM_INACTIVE) ||
- ((!aplic->msimode || (aplic->msimode && !pending)) &&
- ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
- (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))) {
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
return;
}
+ if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
+ (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
+ if (!aplic->msimode || (aplic->msimode && !pending)) {
+ return;
+ }
+ if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
+ (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
+ return;
+ }
+ if (!(aplic->state[irq] & APLIC_ISTATE_INPUT) &&
+ (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH)) {
+ return;
+ }
+ }
+
riscv_aplic_set_pending_raw(aplic, irq, pending);
}
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
index fd68cb8..3dafc00 100644
--- a/hw/misc/stm32l4x5_syscfg.c
+++ b/hw/misc/stm32l4x5_syscfg.c
@@ -27,6 +27,7 @@
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "hw/misc/stm32l4x5_syscfg.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
#define SYSCFG_MEMRMP 0x00
#define SYSCFG_CFGR1 0x04
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 12f9792..09878e7 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -189,13 +189,13 @@
* kernel is uncompressed it will not clobber the initrd. However
* on boards without much RAM we must ensure that we still leave
* enough room for a decent sized initrd, and on boards with large
- * amounts of RAM we must avoid the initrd being so far up in RAM
- * that it is outside lowmem and inaccessible to the kernel.
- * So for boards with less than 256MB of RAM we put the initrd
- * halfway into RAM, and for boards with 256MB of RAM or more we put
- * the initrd at 128MB.
+ * amounts of RAM, we put the initrd at 512MB to allow large kernels
+ * to boot.
+ * So for boards with less than 1GB of RAM we put the initrd
+ * halfway into RAM, and for boards with 1GB of RAM or more we put
+ * the initrd at 512MB.
*/
- start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+ start = kernel_entry + MIN(mem_size / 2, 512 * MiB);
size = load_ramdisk(filename, start, mem_size - start);
if (size == -1) {
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index fb8baf6..0925528 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -174,6 +174,42 @@
aml_append(scope, dev);
}
+/*
+ * Serial Port Console Redirection Table (SPCR)
+ * Rev: 1.07
+ */
+
+static void
+spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
+{
+ AcpiSpcrData serial = {
+ .interface_type = 0, /* 16550 compatible */
+ .base_addr.id = AML_AS_SYSTEM_MEMORY,
+ .base_addr.width = 32,
+ .base_addr.offset = 0,
+ .base_addr.size = 1,
+ .base_addr.addr = s->memmap[VIRT_UART0].base,
+ .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */
+ .pc_interrupt = 0,
+ .interrupt = UART0_IRQ,
+ .baud_rate = 7, /* 15200 */
+ .parity = 0,
+ .stop_bits = 1,
+ .flow_control = 0,
+ .terminal_type = 3, /* ANSI */
+ .language = 0, /* Language */
+ .pci_device_id = 0xffff, /* not a PCI device*/
+ .pci_vendor_id = 0xffff, /* not a PCI device*/
+ .pci_bus = 0,
+ .pci_device = 0,
+ .pci_function = 0,
+ .pci_flags = 0,
+ .pci_segment = 0,
+ };
+
+ build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
+}
+
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -528,11 +564,61 @@
acpi_table_end(linker, &table);
}
+/*
+ * ACPI spec, Revision 6.5+
+ * 5.2.16 System Resource Affinity Table (SRAT)
+ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25
+ * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view
+ */
+static void
+build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms)
+{
+ int i;
+ uint64_t mem_base;
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
+ MachineState *ms = MACHINE(vms);
+ const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
+ AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+ build_append_int_noprefix(table_data, 1, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
+
+ for (i = 0; i < cpu_list->len; ++i) {
+ uint32_t nodeid = cpu_list->cpus[i].props.node_id;
+ /*
+ * 5.2.16.8 RINTC Affinity Structure
+ */
+ build_append_int_noprefix(table_data, 7, 1); /* Type */
+ build_append_int_noprefix(table_data, 20, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+ /* Flags, Table 5-70 */
+ build_append_int_noprefix(table_data, 1 /* Flags: Enabled */, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
+ }
+
+ mem_base = vms->memmap[VIRT_DRAM].base;
+ for (i = 0; i < ms->numa_state->num_nodes; ++i) {
+ if (ms->numa_state->nodes[i].node_mem > 0) {
+ build_srat_memory(table_data, mem_base,
+ ms->numa_state->nodes[i].node_mem, i,
+ MEM_AFFINITY_ENABLED);
+ mem_base += ms->numa_state->nodes[i].node_mem;
+ }
+ }
+
+ acpi_table_end(linker, &table);
+}
+
static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
{
GArray *table_offsets;
unsigned dsdt, xsdt;
GArray *tables_blob = tables->table_data;
+ MachineState *ms = MACHINE(s);
table_offsets = g_array_new(false, true,
sizeof(uint32_t));
@@ -556,15 +642,28 @@
build_rhct(tables_blob, tables->linker, s);
acpi_add_table(table_offsets, tables_blob);
+ spcr_setup(tables_blob, tables->linker, s);
+
+ acpi_add_table(table_offsets, tables_blob);
{
AcpiMcfgInfo mcfg = {
- .base = s->memmap[VIRT_PCIE_MMIO].base,
- .size = s->memmap[VIRT_PCIE_MMIO].size,
+ .base = s->memmap[VIRT_PCIE_ECAM].base,
+ .size = s->memmap[VIRT_PCIE_ECAM].size,
};
build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
s->oem_table_id);
}
+ if (ms->numa_state->num_nodes > 0) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_srat(tables_blob, tables->linker, s);
+ if (ms->numa_state->have_numa_distance) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_slit(tables_blob, tables->linker, ms, s->oem_id,
+ s->oem_table_id);
+ }
+ }
+
/* XSDT is pointed to by RSDP */
xsdt = tables_blob->len;
build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index fd35c74..a094af9 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -48,11 +48,13 @@
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
#include "sysemu/tpm.h"
+#include "sysemu/qtest.h"
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
+#include "hw/virtio/virtio-iommu.h"
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
static bool virt_use_kvm_aia(RISCVVirtState *s)
@@ -60,6 +62,11 @@
return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
}
+static bool virt_aclint_allowed(void)
+{
+ return tcg_enabled() || qtest_enabled();
+}
+
static const MemMapEntry virt_memmap[] = {
[VIRT_DEBUG] = { 0x0, 0x100 },
[VIRT_MROM] = { 0x1000, 0xf000 },
@@ -724,14 +731,12 @@
create_fdt_socket_memory(s, memmap, socket);
- if (tcg_enabled()) {
- if (s->have_aclint) {
- create_fdt_socket_aclint(s, memmap, socket,
- &intc_phandles[phandle_pos]);
- } else {
- create_fdt_socket_clint(s, memmap, socket,
- &intc_phandles[phandle_pos]);
- }
+ if (virt_aclint_allowed() && s->have_aclint) {
+ create_fdt_socket_aclint(s, memmap, socket,
+ &intc_phandles[phandle_pos]);
+ } else if (tcg_enabled()) {
+ create_fdt_socket_clint(s, memmap, socket,
+ &intc_phandles[phandle_pos]);
}
}
@@ -826,7 +831,6 @@
name = g_strdup_printf("/soc/pci@%lx",
(long) memmap[VIRT_PCIE_ECAM].base);
- qemu_fdt_add_subnode(ms->fdt, name);
qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
FDT_PCI_ADDR_CELLS);
qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
@@ -972,6 +976,34 @@
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
}
+static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
+{
+ const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
+ void *fdt = MACHINE(s)->fdt;
+ uint32_t iommu_phandle;
+ g_autofree char *iommu_node = NULL;
+ g_autofree char *pci_node = NULL;
+
+ pci_node = g_strdup_printf("/soc/pci@%lx",
+ (long) virt_memmap[VIRT_PCIE_ECAM].base);
+ iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node,
+ PCI_SLOT(bdf), PCI_FUNC(bdf));
+ iommu_phandle = qemu_fdt_alloc_phandle(fdt);
+
+ qemu_fdt_add_subnode(fdt, iommu_node);
+
+ qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat));
+ qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg",
+ 1, bdf << 8, 1, 0, 1, 0,
+ 1, 0, 1, 0);
+ qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
+ qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
+
+ qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
+ 0, iommu_phandle, 0, bdf,
+ bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
+}
+
static void finalize_fdt(RISCVVirtState *s)
{
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
@@ -996,6 +1028,7 @@
{
MachineState *ms = MACHINE(s);
uint8_t rng_seed[32];
+ g_autofree char *name = NULL;
ms->fdt = create_device_tree(&s->fdt_size);
if (!ms->fdt) {
@@ -1014,6 +1047,13 @@
qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
+ /*
+ * The "/soc/pci@..." node is needed for PCIE hotplugs
+ * that might happen before finalize_fdt().
+ */
+ name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base);
+ qemu_fdt_add_subnode(ms->fdt, name);
+
qemu_fdt_add_subnode(ms->fdt, "/chosen");
/* Pass seed to RNG */
@@ -1373,7 +1413,7 @@
exit(1);
}
- if (!tcg_enabled() && s->have_aclint) {
+ if (!virt_aclint_allowed() && s->have_aclint) {
error_report("'aclint' is only available with TCG acceleration");
exit(1);
}
@@ -1410,23 +1450,22 @@
hart_count, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
- if (tcg_enabled()) {
- if (s->have_aclint) {
- if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
- /* Per-socket ACLINT MTIMER */
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+ if (virt_aclint_allowed() && s->have_aclint) {
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+ /* Per-socket ACLINT MTIMER */
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
base_hartid, hart_count,
RISCV_ACLINT_DEFAULT_MTIMECMP,
RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
- } else {
- /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
- riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
+ } else {
+ /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
+ riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
i * memmap[VIRT_CLINT].size,
base_hartid, hart_count, false);
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
i * memmap[VIRT_CLINT].size +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
@@ -1434,21 +1473,20 @@
RISCV_ACLINT_DEFAULT_MTIMECMP,
RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
- riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
+ riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
i * memmap[VIRT_ACLINT_SSWI].size,
base_hartid, hart_count, true);
- }
- } else {
- /* Per-socket SiFive CLINT */
- riscv_aclint_swi_create(
+ }
+ } else if (tcg_enabled()) {
+ /* Per-socket SiFive CLINT */
+ riscv_aclint_swi_create(
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
base_hartid, hart_count, false);
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
- }
}
/* Per-socket interrupt controller */
@@ -1673,7 +1711,8 @@
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
- if (device_is_dynamic_sysbus(mc, dev)) {
+ if (device_is_dynamic_sysbus(mc, dev) ||
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
return HOTPLUG_HANDLER(machine);
}
return NULL;
@@ -1692,6 +1731,10 @@
SYS_BUS_DEVICE(dev));
}
}
+
+ if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
+ create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
+ }
}
static void virt_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c
index e037acd..ffcc0aa 100644
--- a/hw/rtc/sun4v-rtc.c
+++ b/hw/rtc/sun4v-rtc.c
@@ -5,7 +5,7 @@
*
* Copyright (c) 2016 Artyom Tarasenko
*
- * This code is licensed under the GNU GPL v3 or (at your option) any later
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
* version.
*/
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 2b42e41..0e6e82b 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -90,6 +90,39 @@
unsigned *xdsdt_tbl_offset;
} AcpiFadtData;
+typedef struct AcpiGas {
+ uint8_t id; /* Address space ID */
+ uint8_t width; /* Register bit width */
+ uint8_t offset; /* Register bit offset */
+ uint8_t size; /* Access size */
+ uint64_t addr; /* Address */
+} AcpiGas;
+
+/* SPCR (Serial Port Console Redirection table) */
+typedef struct AcpiSpcrData {
+ uint8_t interface_type;
+ uint8_t reserved[3];
+ struct AcpiGas base_addr;
+ uint8_t interrupt_type;
+ uint8_t pc_interrupt;
+ uint32_t interrupt; /* Global system interrupt */
+ uint8_t baud_rate;
+ uint8_t parity;
+ uint8_t stop_bits;
+ uint8_t flow_control;
+ uint8_t terminal_type;
+ uint8_t language;
+ uint8_t reserved1;
+ uint16_t pci_device_id; /* Must be 0xffff if not PCI device */
+ uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */
+ uint8_t pci_bus;
+ uint8_t pci_device;
+ uint8_t pci_function;
+ uint32_t pci_flags;
+ uint8_t pci_segment;
+ uint32_t reserved2;
+} AcpiSpcrData;
+
#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index ff2a310..a378415 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -497,4 +497,8 @@
void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
const char *oem_id, const char *oem_table_id);
+
+void build_spcr(GArray *table_data, BIOSLinker *linker,
+ const AcpiSpcrData *f, const uint8_t rev,
+ const char *oem_id, const char *oem_table_id);
#endif
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
index af67b08..ee5f362 100644
--- a/include/hw/arm/stm32l4x5_soc.h
+++ b/include/hw/arm/stm32l4x5_soc.h
@@ -30,6 +30,7 @@
#include "hw/misc/stm32l4x5_syscfg.h"
#include "hw/misc/stm32l4x5_exti.h"
#include "hw/misc/stm32l4x5_rcc.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
#include "qom/object.h"
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
@@ -49,6 +50,7 @@
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
Stm32l4x5SyscfgState syscfg;
Stm32l4x5RccState rcc;
+ Stm32l4x5GpioState gpio[NUM_GPIOS];
MemoryRegion sram1;
MemoryRegion sram2;
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
new file mode 100644
index 0000000..878bd19
--- /dev/null
+++ b/include/hw/gpio/stm32l4x5_gpio.h
@@ -0,0 +1,71 @@
+/*
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
+ *
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#ifndef HW_STM32L4X5_GPIO_H
+#define HW_STM32L4X5_GPIO_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
+
+#define NUM_GPIOS 8
+#define GPIO_NUM_PINS 16
+
+struct Stm32l4x5GpioState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ /* GPIO registers */
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t idr;
+ uint32_t odr;
+ uint32_t lckr;
+ uint32_t afrl;
+ uint32_t afrh;
+ uint32_t ascr;
+
+ /* GPIO registers reset values */
+ uint32_t moder_reset;
+ uint32_t ospeedr_reset;
+ uint32_t pupdr_reset;
+
+ /*
+ * External driving of pins.
+ * The pins can be set externally through the device
+ * anonymous input GPIOs lines under certain conditions.
+ * The pin must not be in push-pull output mode,
+ * and can't be set high in open-drain mode.
+ * Pins driven externally and configured to
+ * output mode will in general be "disconnected"
+ * (see `get_gpio_pinmask_to_disconnect()`)
+ */
+ uint16_t disconnected_pins;
+ uint16_t pins_connected_high;
+
+ char *name;
+ Clock *clk;
+ qemu_irq pin[GPIO_NUM_PINS];
+};
+
+#endif
diff --git a/include/hw/hyperv/dynmem-proto.h b/include/hw/hyperv/dynmem-proto.h
index a657786..68b8b60 100644
--- a/include/hw/hyperv/dynmem-proto.h
+++ b/include/hw/hyperv/dynmem-proto.h
@@ -328,7 +328,8 @@
/*
* Hot add request message. Message sent from the host to the guest.
*
- * mem_range: Memory range to hot add.
+ * range: Memory range to hot add.
+ * region: Explicit hot add memory region for guest to use. Optional.
*
*/
@@ -337,6 +338,12 @@
union dm_mem_page_range range;
} QEMU_PACKED;
+struct dm_hot_add_with_region {
+ struct dm_header hdr;
+ union dm_mem_page_range range;
+ union dm_mem_page_range region;
+} QEMU_PACKED;
+
/*
* Hot add response message.
* This message is sent by the guest to report the status of a hot add request.
diff --git a/include/hw/hyperv/hyperv.h b/include/hw/hyperv/hyperv.h
index 015c352..d717b4e 100644
--- a/include/hw/hyperv/hyperv.h
+++ b/include/hw/hyperv/hyperv.h
@@ -139,4 +139,8 @@
} HvSynDbgMsg;
typedef uint16_t (*HvSynDbgHandler)(void *context, HvSynDbgMsg *msg);
void hyperv_set_syndbg_handler(HvSynDbgHandler handler, void *context);
+
+bool hyperv_are_vmbus_recommended_features_enabled(void);
+void hyperv_set_vmbus_recommended_features_enabled(void);
+
#endif
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
index 29c3522..23bb564 100644
--- a/include/hw/misc/stm32l4x5_syscfg.h
+++ b/include/hw/misc/stm32l4x5_syscfg.h
@@ -26,12 +26,11 @@
#include "hw/sysbus.h"
#include "qom/object.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
-#define NUM_GPIOS 8
-#define GPIO_NUM_PINS 16
#define SYSCFG_NUM_EXTICR 4
struct Stm32l4x5SyscfgState {
diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h
index fc54dfc..26a9eb6 100644
--- a/include/hw/rtc/sun4v-rtc.h
+++ b/include/hw/rtc/sun4v-rtc.h
@@ -5,7 +5,7 @@
*
* Copyright (c) 2016 Artyom Tarasenko
*
- * This code is licensed under the GNU GPL v3 or (at your option) any later
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
* version.
*/
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h
index 3afb701..b729170 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -53,7 +53,7 @@
* Format modifiers may change any property of the buffer, including the number
* of planes and/or the required allocation size. Format modifiers are
* vendor-namespaced, and as such the relationship between a fourcc code and a
- * modifier is specific to the modifer being used. For example, some modifiers
+ * modifier is specific to the modifier being used. For example, some modifiers
* may preserve meaning - such as number of planes - from the fourcc code,
* whereas others may not.
*
@@ -78,7 +78,7 @@
* format.
* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
* see modifiers as opaque tokens they can check for equality and intersect.
- * These users musn't need to know to reason about the modifier value
+ * These users mustn't need to know to reason about the modifier value
* (i.e. they are not expected to extract information out of the modifier).
*
* Vendors should document their modifier usage in as much detail as
@@ -539,7 +539,7 @@
* This is a tiled layout using 4Kb tiles in row-major layout.
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
* are arranged in four groups (two wide, two high) with column-major layout.
- * Each group therefore consits out of four 256 byte units, which are also laid
+ * Each group therefore consists out of four 256 byte units, which are also laid
* out as 2x2 column-major.
* 256 byte units are made out of four 64 byte blocks of pixels, producing
* either a square block or a 2:1 unit.
@@ -1102,7 +1102,7 @@
*/
/*
- * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
+ * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
* modifiers) denote the category for modifiers. Currently we have three
* categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
* sixteen different categories.
@@ -1418,7 +1418,7 @@
* Amlogic FBC Memory Saving mode
*
* Indicates the storage is packed when pixel size is multiple of word
- * boudaries, i.e. 8bit should be stored in this mode to save allocation
+ * boundaries, i.e. 8bit should be stored in this mode to save allocation
* memory.
*
* This mode reduces body layout to 3072 bytes per 64x32 superblock with
diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h
index 99fcddf..dfb54ef 100644
--- a/include/standard-headers/linux/ethtool.h
+++ b/include/standard-headers/linux/ethtool.h
@@ -1266,6 +1266,8 @@
* hardware hash key.
* @hfunc: Defines the current RSS hash function used by HW (or to be set to).
* Valid values are one of the %ETH_RSS_HASH_*.
+ * @input_xfrm: Defines how the input data is transformed. Valid values are one
+ * of %RXH_XFRM_*.
* @rsvd8: Reserved for future use; see the note on reserved space.
* @rsvd32: Reserved for future use; see the note on reserved space.
* @rss_config: RX ring/queue index for each hash value i.e., indirection table
@@ -1285,7 +1287,8 @@
uint32_t indir_size;
uint32_t key_size;
uint8_t hfunc;
- uint8_t rsvd8[3];
+ uint8_t input_xfrm;
+ uint8_t rsvd8[2];
uint32_t rsvd32;
uint32_t rss_config[];
};
@@ -1992,6 +1995,15 @@
#define WOL_MODE_COUNT 8
+/* RSS hash function data
+ * XOR the corresponding source and destination fields of each specified
+ * protocol. Both copies of the XOR'ed fields are fed into the RSS and RXHASH
+ * calculation. Note that this XORing reduces the input set entropy and could
+ * be exploited to reduce the RSS queue spread.
+ */
+#define RXH_XFRM_SYM_XOR (1 << 0)
+#define RXH_XFRM_NO_CHANGE 0xff
+
/* L2-L4 network traffic flow types */
#define TCP_V4_FLOW 0x01 /* hash or spec (tcp_ip4_spec) */
#define UDP_V4_FLOW 0x02 /* hash or spec (udp_ip4_spec) */
@@ -2128,18 +2140,6 @@
* refused. For drivers: ignore this field (use kernel's
* __ETHTOOL_LINK_MODE_MASK_NBITS instead), any change to it will
* be overwritten by kernel.
- * @supported: Bitmap with each bit meaning given by
- * %ethtool_link_mode_bit_indices for the link modes, physical
- * connectors and other link features for which the interface
- * supports autonegotiation or auto-detection. Read-only.
- * @advertising: Bitmap with each bit meaning given by
- * %ethtool_link_mode_bit_indices for the link modes, physical
- * connectors and other link features that are advertised through
- * autonegotiation or enabled for auto-detection.
- * @lp_advertising: Bitmap with each bit meaning given by
- * %ethtool_link_mode_bit_indices for the link modes, and other
- * link features that the link partner advertised through
- * autonegotiation; 0 if unknown or not applicable. Read-only.
* @transceiver: Used to distinguish different possible PHY types,
* reported consistently by PHYLIB. Read-only.
* @master_slave_cfg: Master/slave port mode.
@@ -2181,6 +2181,21 @@
* %set_link_ksettings() should validate all fields other than @cmd
* and @link_mode_masks_nwords that are not described as read-only or
* deprecated, and must ignore all fields described as read-only.
+ *
+ * @link_mode_masks is divided into three bitfields, each of length
+ * @link_mode_masks_nwords:
+ * - supported: Bitmap with each bit meaning given by
+ * %ethtool_link_mode_bit_indices for the link modes, physical
+ * connectors and other link features for which the interface
+ * supports autonegotiation or auto-detection. Read-only.
+ * - advertising: Bitmap with each bit meaning given by
+ * %ethtool_link_mode_bit_indices for the link modes, physical
+ * connectors and other link features that are advertised through
+ * autonegotiation or enabled for auto-detection.
+ * - lp_advertising: Bitmap with each bit meaning given by
+ * %ethtool_link_mode_bit_indices for the link modes, and other
+ * link features that the link partner advertised through
+ * autonegotiation; 0 if unknown or not applicable. Read-only.
*/
struct ethtool_link_settings {
uint32_t cmd;
diff --git a/include/standard-headers/linux/virtio_config.h b/include/standard-headers/linux/virtio_config.h
index bfd1ca6..45be0fa 100644
--- a/include/standard-headers/linux/virtio_config.h
+++ b/include/standard-headers/linux/virtio_config.h
@@ -52,7 +52,7 @@
* rest are per-device feature bits.
*/
#define VIRTIO_TRANSPORT_F_START 28
-#define VIRTIO_TRANSPORT_F_END 41
+#define VIRTIO_TRANSPORT_F_END 42
#ifndef VIRTIO_CONFIG_NO_LEGACY
/* Do we get callbacks when the ring is completely used, even if we've
@@ -112,4 +112,10 @@
* This feature indicates that the driver can reset a queue individually.
*/
#define VIRTIO_F_RING_RESET 40
+
+/*
+ * This feature indicates that the device support administration virtqueues.
+ */
+#define VIRTIO_F_ADMIN_VQ 41
+
#endif /* _LINUX_VIRTIO_CONFIG_H */
diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard-headers/linux/virtio_pci.h
index b7fdfd0..3e2bc2c 100644
--- a/include/standard-headers/linux/virtio_pci.h
+++ b/include/standard-headers/linux/virtio_pci.h
@@ -175,6 +175,9 @@
uint16_t queue_notify_data; /* read-write */
uint16_t queue_reset; /* read-write */
+
+ uint16_t admin_queue_index; /* read-only */
+ uint16_t admin_queue_num; /* read-only */
};
/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
@@ -215,7 +218,72 @@
#define VIRTIO_PCI_COMMON_Q_USEDHI 52
#define VIRTIO_PCI_COMMON_Q_NDATA 56
#define VIRTIO_PCI_COMMON_Q_RESET 58
+#define VIRTIO_PCI_COMMON_ADM_Q_IDX 60
+#define VIRTIO_PCI_COMMON_ADM_Q_NUM 62
#endif /* VIRTIO_PCI_NO_MODERN */
+/* Admin command status. */
+#define VIRTIO_ADMIN_STATUS_OK 0
+
+/* Admin command opcode. */
+#define VIRTIO_ADMIN_CMD_LIST_QUERY 0x0
+#define VIRTIO_ADMIN_CMD_LIST_USE 0x1
+
+/* Admin command group type. */
+#define VIRTIO_ADMIN_GROUP_TYPE_SRIOV 0x1
+
+/* Transitional device admin command. */
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE 0x2
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ 0x3
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE 0x4
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ 0x5
+#define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO 0x6
+
+struct QEMU_PACKED virtio_admin_cmd_hdr {
+ uint16_t opcode;
+ /*
+ * 1 - SR-IOV
+ * 2-65535 - reserved
+ */
+ uint16_t group_type;
+ /* Unused, reserved for future extensions. */
+ uint8_t reserved1[12];
+ uint64_t group_member_id;
+};
+
+struct QEMU_PACKED virtio_admin_cmd_status {
+ uint16_t status;
+ uint16_t status_qualifier;
+ /* Unused, reserved for future extensions. */
+ uint8_t reserved2[4];
+};
+
+struct QEMU_PACKED virtio_admin_cmd_legacy_wr_data {
+ uint8_t offset; /* Starting offset of the register(s) to write. */
+ uint8_t reserved[7];
+ uint8_t registers[];
+};
+
+struct QEMU_PACKED virtio_admin_cmd_legacy_rd_data {
+ uint8_t offset; /* Starting offset of the register(s) to read. */
+};
+
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_END 0
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_DEV 0x1
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM 0x2
+
+#define VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO 4
+
+struct QEMU_PACKED virtio_admin_cmd_notify_info_data {
+ uint8_t flags; /* 0 = end of list, 1 = owner device, 2 = member device */
+ uint8_t bar; /* BAR of the member or the owner device */
+ uint8_t padding[6];
+ uint64_t offset; /* Offset within bar. */
+};
+
+struct virtio_admin_cmd_notify_info_result {
+ struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO];
+};
+
#endif
diff --git a/include/standard-headers/linux/virtio_pmem.h b/include/standard-headers/linux/virtio_pmem.h
index fc029de..1a2576d 100644
--- a/include/standard-headers/linux/virtio_pmem.h
+++ b/include/standard-headers/linux/virtio_pmem.h
@@ -14,6 +14,13 @@
#include "standard-headers/linux/virtio_ids.h"
#include "standard-headers/linux/virtio_config.h"
+/* Feature bits */
+/* guest physical address range will be indicated as shared memory region 0 */
+#define VIRTIO_PMEM_F_SHMEM_REGION 0
+
+/* shmid of the shared memory region corresponding to the pmem */
+#define VIRTIO_PMEM_SHMEM_REGION_ID 0
+
struct virtio_pmem_config {
uint64_t start;
uint64_t size;
diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h
index 756b013..75f0096 100644
--- a/linux-headers/asm-generic/unistd.h
+++ b/linux-headers/asm-generic/unistd.h
@@ -829,8 +829,21 @@
#define __NR_futex_requeue 456
__SYSCALL(__NR_futex_requeue, sys_futex_requeue)
+#define __NR_statmount 457
+__SYSCALL(__NR_statmount, sys_statmount)
+
+#define __NR_listmount 458
+__SYSCALL(__NR_listmount, sys_listmount)
+
+#define __NR_lsm_get_self_attr 459
+__SYSCALL(__NR_lsm_get_self_attr, sys_lsm_get_self_attr)
+#define __NR_lsm_set_self_attr 460
+__SYSCALL(__NR_lsm_set_self_attr, sys_lsm_set_self_attr)
+#define __NR_lsm_list_modules 461
+__SYSCALL(__NR_lsm_list_modules, sys_lsm_list_modules)
+
#undef __NR_syscalls
-#define __NR_syscalls 457
+#define __NR_syscalls 462
/*
* 32 bit systems traditionally used different
diff --git a/linux-headers/asm-mips/mman.h b/linux-headers/asm-mips/mman.h
index c6e1fc7..9c48d9a 100644
--- a/linux-headers/asm-mips/mman.h
+++ b/linux-headers/asm-mips/mman.h
@@ -88,7 +88,7 @@
#define MADV_HUGEPAGE 14 /* Worth backing with hugepages */
#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */
-#define MADV_DONTDUMP 16 /* Explicity exclude from the core dump,
+#define MADV_DONTDUMP 16 /* Explicitly exclude from core dump,
overrides the coredump filter bits */
#define MADV_DODUMP 17 /* Clear the MADV_NODUMP flag */
diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h
index 994b6f0..ce2e050 100644
--- a/linux-headers/asm-mips/unistd_n32.h
+++ b/linux-headers/asm-mips/unistd_n32.h
@@ -385,5 +385,10 @@
#define __NR_futex_wake (__NR_Linux + 454)
#define __NR_futex_wait (__NR_Linux + 455)
#define __NR_futex_requeue (__NR_Linux + 456)
+#define __NR_statmount (__NR_Linux + 457)
+#define __NR_listmount (__NR_Linux + 458)
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
+#define __NR_lsm_list_modules (__NR_Linux + 461)
#endif /* _ASM_UNISTD_N32_H */
diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h
index 41dcf58..5bfb373 100644
--- a/linux-headers/asm-mips/unistd_n64.h
+++ b/linux-headers/asm-mips/unistd_n64.h
@@ -361,5 +361,10 @@
#define __NR_futex_wake (__NR_Linux + 454)
#define __NR_futex_wait (__NR_Linux + 455)
#define __NR_futex_requeue (__NR_Linux + 456)
+#define __NR_statmount (__NR_Linux + 457)
+#define __NR_listmount (__NR_Linux + 458)
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
+#define __NR_lsm_list_modules (__NR_Linux + 461)
#endif /* _ASM_UNISTD_N64_H */
diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h
index ae9d334..02eaecd 100644
--- a/linux-headers/asm-mips/unistd_o32.h
+++ b/linux-headers/asm-mips/unistd_o32.h
@@ -431,5 +431,10 @@
#define __NR_futex_wake (__NR_Linux + 454)
#define __NR_futex_wait (__NR_Linux + 455)
#define __NR_futex_requeue (__NR_Linux + 456)
+#define __NR_statmount (__NR_Linux + 457)
+#define __NR_listmount (__NR_Linux + 458)
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
+#define __NR_lsm_list_modules (__NR_Linux + 461)
#endif /* _ASM_UNISTD_O32_H */
diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h
index b9b23d6..bbab08d 100644
--- a/linux-headers/asm-powerpc/unistd_32.h
+++ b/linux-headers/asm-powerpc/unistd_32.h
@@ -438,6 +438,11 @@
#define __NR_futex_wake 454
#define __NR_futex_wait 455
#define __NR_futex_requeue 456
+#define __NR_statmount 457
+#define __NR_listmount 458
+#define __NR_lsm_get_self_attr 459
+#define __NR_lsm_set_self_attr 460
+#define __NR_lsm_list_modules 461
#endif /* _ASM_UNISTD_32_H */
diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h
index cbb4b3e..af34cde 100644
--- a/linux-headers/asm-powerpc/unistd_64.h
+++ b/linux-headers/asm-powerpc/unistd_64.h
@@ -410,6 +410,11 @@
#define __NR_futex_wake 454
#define __NR_futex_wait 455
#define __NR_futex_requeue 456
+#define __NR_statmount 457
+#define __NR_listmount 458
+#define __NR_lsm_get_self_attr 459
+#define __NR_lsm_set_self_attr 460
+#define __NR_lsm_list_modules 461
#endif /* _ASM_UNISTD_64_H */
diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
index 60d3b21..7499e88 100644
--- a/linux-headers/asm-riscv/kvm.h
+++ b/linux-headers/asm-riscv/kvm.h
@@ -139,6 +139,33 @@
KVM_RISCV_ISA_EXT_ZIHPM,
KVM_RISCV_ISA_EXT_SMSTATEEN,
KVM_RISCV_ISA_EXT_ZICOND,
+ KVM_RISCV_ISA_EXT_ZBC,
+ KVM_RISCV_ISA_EXT_ZBKB,
+ KVM_RISCV_ISA_EXT_ZBKC,
+ KVM_RISCV_ISA_EXT_ZBKX,
+ KVM_RISCV_ISA_EXT_ZKND,
+ KVM_RISCV_ISA_EXT_ZKNE,
+ KVM_RISCV_ISA_EXT_ZKNH,
+ KVM_RISCV_ISA_EXT_ZKR,
+ KVM_RISCV_ISA_EXT_ZKSED,
+ KVM_RISCV_ISA_EXT_ZKSH,
+ KVM_RISCV_ISA_EXT_ZKT,
+ KVM_RISCV_ISA_EXT_ZVBB,
+ KVM_RISCV_ISA_EXT_ZVBC,
+ KVM_RISCV_ISA_EXT_ZVKB,
+ KVM_RISCV_ISA_EXT_ZVKG,
+ KVM_RISCV_ISA_EXT_ZVKNED,
+ KVM_RISCV_ISA_EXT_ZVKNHA,
+ KVM_RISCV_ISA_EXT_ZVKNHB,
+ KVM_RISCV_ISA_EXT_ZVKSED,
+ KVM_RISCV_ISA_EXT_ZVKSH,
+ KVM_RISCV_ISA_EXT_ZVKT,
+ KVM_RISCV_ISA_EXT_ZFH,
+ KVM_RISCV_ISA_EXT_ZFHMIN,
+ KVM_RISCV_ISA_EXT_ZIHINTNTL,
+ KVM_RISCV_ISA_EXT_ZVFH,
+ KVM_RISCV_ISA_EXT_ZVFHMIN,
+ KVM_RISCV_ISA_EXT_ZFA,
KVM_RISCV_ISA_EXT_MAX,
};
@@ -157,9 +184,16 @@
KVM_RISCV_SBI_EXT_EXPERIMENTAL,
KVM_RISCV_SBI_EXT_VENDOR,
KVM_RISCV_SBI_EXT_DBCN,
+ KVM_RISCV_SBI_EXT_STA,
KVM_RISCV_SBI_EXT_MAX,
};
+/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_sbi_sta {
+ unsigned long shmem_lo;
+ unsigned long shmem_hi;
+};
+
/* Possible states for kvm_riscv_timer */
#define KVM_RISCV_TIMER_STATE_OFF 0
#define KVM_RISCV_TIMER_STATE_ON 1
@@ -241,6 +275,12 @@
#define KVM_REG_RISCV_VECTOR_REG(n) \
((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
+/* Registers for specific SBI extensions are mapped as type 10 */
+#define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_STA_REG(name) \
+ (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
+
/* Device Control API: RISC-V AIA */
#define KVM_DEV_RISCV_APLIC_ALIGN 0x1000
#define KVM_DEV_RISCV_APLIC_SIZE 0x4000
diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h
index c093e6d..a3ece69 100644
--- a/linux-headers/asm-s390/unistd_32.h
+++ b/linux-headers/asm-s390/unistd_32.h
@@ -429,5 +429,10 @@
#define __NR_futex_wake 454
#define __NR_futex_wait 455
#define __NR_futex_requeue 456
+#define __NR_statmount 457
+#define __NR_listmount 458
+#define __NR_lsm_get_self_attr 459
+#define __NR_lsm_set_self_attr 460
+#define __NR_lsm_list_modules 461
#endif /* _ASM_S390_UNISTD_32_H */
diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h
index 114c056..8c5fd93 100644
--- a/linux-headers/asm-s390/unistd_64.h
+++ b/linux-headers/asm-s390/unistd_64.h
@@ -377,5 +377,10 @@
#define __NR_futex_wake 454
#define __NR_futex_wait 455
#define __NR_futex_requeue 456
+#define __NR_statmount 457
+#define __NR_listmount 458
+#define __NR_lsm_get_self_attr 459
+#define __NR_lsm_set_self_attr 460
+#define __NR_lsm_list_modules 461
#endif /* _ASM_S390_UNISTD_64_H */
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index 2b3a8f7..003fb74 100644
--- a/linux-headers/asm-x86/kvm.h
+++ b/linux-headers/asm-x86/kvm.h
@@ -560,4 +560,7 @@
/* x86-specific KVM_EXIT_HYPERCALL flags. */
#define KVM_EXIT_HYPERCALL_LONG_MODE BIT(0)
+#define KVM_X86_DEFAULT_VM 0
+#define KVM_X86_SW_PROTECTED_VM 1
+
#endif /* _ASM_X86_KVM_H */
diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h
index 329649c..5c9c329 100644
--- a/linux-headers/asm-x86/unistd_32.h
+++ b/linux-headers/asm-x86/unistd_32.h
@@ -447,6 +447,11 @@
#define __NR_futex_wake 454
#define __NR_futex_wait 455
#define __NR_futex_requeue 456
+#define __NR_statmount 457
+#define __NR_listmount 458
+#define __NR_lsm_get_self_attr 459
+#define __NR_lsm_set_self_attr 460
+#define __NR_lsm_list_modules 461
#endif /* _ASM_UNISTD_32_H */
diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h
index 4583606..d9aab7a 100644
--- a/linux-headers/asm-x86/unistd_64.h
+++ b/linux-headers/asm-x86/unistd_64.h
@@ -369,6 +369,11 @@
#define __NR_futex_wake 454
#define __NR_futex_wait 455
#define __NR_futex_requeue 456
+#define __NR_statmount 457
+#define __NR_listmount 458
+#define __NR_lsm_get_self_attr 459
+#define __NR_lsm_set_self_attr 460
+#define __NR_lsm_list_modules 461
#endif /* _ASM_UNISTD_64_H */
diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h
index 146d74d..63cdd1e 100644
--- a/linux-headers/asm-x86/unistd_x32.h
+++ b/linux-headers/asm-x86/unistd_x32.h
@@ -321,6 +321,11 @@
#define __NR_futex_wake (__X32_SYSCALL_BIT + 454)
#define __NR_futex_wait (__X32_SYSCALL_BIT + 455)
#define __NR_futex_requeue (__X32_SYSCALL_BIT + 456)
+#define __NR_statmount (__X32_SYSCALL_BIT + 457)
+#define __NR_listmount (__X32_SYSCALL_BIT + 458)
+#define __NR_lsm_get_self_attr (__X32_SYSCALL_BIT + 459)
+#define __NR_lsm_set_self_attr (__X32_SYSCALL_BIT + 460)
+#define __NR_lsm_list_modules (__X32_SYSCALL_BIT + 461)
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
diff --git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommufd.h
index 806d98d..72e8f4b 100644
--- a/linux-headers/linux/iommufd.h
+++ b/linux-headers/linux/iommufd.h
@@ -49,6 +49,7 @@
IOMMUFD_CMD_GET_HW_INFO,
IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING,
IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP,
+ IOMMUFD_CMD_HWPT_INVALIDATE,
};
/**
@@ -613,4 +614,82 @@
#define IOMMU_HWPT_GET_DIRTY_BITMAP _IO(IOMMUFD_TYPE, \
IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP)
+/**
+ * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
+ * Data Type
+ * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
+ */
+enum iommu_hwpt_invalidate_data_type {
+ IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
+};
+
+/**
+ * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
+ * stage-1 cache invalidation
+ * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
+ * to all-levels page structure cache or just
+ * the leaf PTE cache.
+ */
+enum iommu_hwpt_vtd_s1_invalidate_flags {
+ IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0,
+};
+
+/**
+ * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
+ * (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
+ * @addr: The start address of the range to be invalidated. It needs to
+ * be 4KB aligned.
+ * @npages: Number of contiguous 4K pages to be invalidated.
+ * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
+ * @__reserved: Must be 0
+ *
+ * The Intel VT-d specific invalidation data for user-managed stage-1 cache
+ * invalidation in nested translation. Userspace uses this structure to
+ * tell the impacted cache scope after modifying the stage-1 page table.
+ *
+ * Invalidating all the caches related to the page table by setting @addr
+ * to be 0 and @npages to be U64_MAX.
+ *
+ * The device TLB will be invalidated automatically if ATS is enabled.
+ */
+struct iommu_hwpt_vtd_s1_invalidate {
+ __aligned_u64 addr;
+ __aligned_u64 npages;
+ __u32 flags;
+ __u32 __reserved;
+};
+
+/**
+ * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
+ * @size: sizeof(struct iommu_hwpt_invalidate)
+ * @hwpt_id: ID of a nested HWPT for cache invalidation
+ * @data_uptr: User pointer to an array of driver-specific cache invalidation
+ * data.
+ * @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the data
+ * type of all the entries in the invalidation request array. It
+ * should be a type supported by the hwpt pointed by @hwpt_id.
+ * @entry_len: Length (in bytes) of a request entry in the request array
+ * @entry_num: Input the number of cache invalidation requests in the array.
+ * Output the number of requests successfully handled by kernel.
+ * @__reserved: Must be 0.
+ *
+ * Invalidate the iommu cache for user-managed page table. Modifications on a
+ * user-managed page table should be followed by this operation to sync cache.
+ * Each ioctl can support one or more cache invalidation requests in the array
+ * that has a total size of @entry_len * @entry_num.
+ *
+ * An empty invalidation request array by setting @entry_num==0 is allowed, and
+ * @entry_len and @data_uptr would be ignored in this case. This can be used to
+ * check if the given @data_type is supported or not by kernel.
+ */
+struct iommu_hwpt_invalidate {
+ __u32 size;
+ __u32 hwpt_id;
+ __aligned_u64 data_uptr;
+ __u32 data_type;
+ __u32 entry_len;
+ __u32 entry_num;
+ __u32 __reserved;
+};
+#define IOMMU_HWPT_INVALIDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_INVALIDATE)
#endif
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 549fea3..1783922 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -16,76 +16,6 @@
#define KVM_API_VERSION 12
-/* *** Deprecated interfaces *** */
-
-#define KVM_TRC_SHIFT 16
-
-#define KVM_TRC_ENTRYEXIT (1 << KVM_TRC_SHIFT)
-#define KVM_TRC_HANDLER (1 << (KVM_TRC_SHIFT + 1))
-
-#define KVM_TRC_VMENTRY (KVM_TRC_ENTRYEXIT + 0x01)
-#define KVM_TRC_VMEXIT (KVM_TRC_ENTRYEXIT + 0x02)
-#define KVM_TRC_PAGE_FAULT (KVM_TRC_HANDLER + 0x01)
-
-#define KVM_TRC_HEAD_SIZE 12
-#define KVM_TRC_CYCLE_SIZE 8
-#define KVM_TRC_EXTRA_MAX 7
-
-#define KVM_TRC_INJ_VIRQ (KVM_TRC_HANDLER + 0x02)
-#define KVM_TRC_REDELIVER_EVT (KVM_TRC_HANDLER + 0x03)
-#define KVM_TRC_PEND_INTR (KVM_TRC_HANDLER + 0x04)
-#define KVM_TRC_IO_READ (KVM_TRC_HANDLER + 0x05)
-#define KVM_TRC_IO_WRITE (KVM_TRC_HANDLER + 0x06)
-#define KVM_TRC_CR_READ (KVM_TRC_HANDLER + 0x07)
-#define KVM_TRC_CR_WRITE (KVM_TRC_HANDLER + 0x08)
-#define KVM_TRC_DR_READ (KVM_TRC_HANDLER + 0x09)
-#define KVM_TRC_DR_WRITE (KVM_TRC_HANDLER + 0x0A)
-#define KVM_TRC_MSR_READ (KVM_TRC_HANDLER + 0x0B)
-#define KVM_TRC_MSR_WRITE (KVM_TRC_HANDLER + 0x0C)
-#define KVM_TRC_CPUID (KVM_TRC_HANDLER + 0x0D)
-#define KVM_TRC_INTR (KVM_TRC_HANDLER + 0x0E)
-#define KVM_TRC_NMI (KVM_TRC_HANDLER + 0x0F)
-#define KVM_TRC_VMMCALL (KVM_TRC_HANDLER + 0x10)
-#define KVM_TRC_HLT (KVM_TRC_HANDLER + 0x11)
-#define KVM_TRC_CLTS (KVM_TRC_HANDLER + 0x12)
-#define KVM_TRC_LMSW (KVM_TRC_HANDLER + 0x13)
-#define KVM_TRC_APIC_ACCESS (KVM_TRC_HANDLER + 0x14)
-#define KVM_TRC_TDP_FAULT (KVM_TRC_HANDLER + 0x15)
-#define KVM_TRC_GTLB_WRITE (KVM_TRC_HANDLER + 0x16)
-#define KVM_TRC_STLB_WRITE (KVM_TRC_HANDLER + 0x17)
-#define KVM_TRC_STLB_INVAL (KVM_TRC_HANDLER + 0x18)
-#define KVM_TRC_PPC_INSTR (KVM_TRC_HANDLER + 0x19)
-
-struct kvm_user_trace_setup {
- __u32 buf_size;
- __u32 buf_nr;
-};
-
-#define __KVM_DEPRECATED_MAIN_W_0x06 \
- _IOW(KVMIO, 0x06, struct kvm_user_trace_setup)
-#define __KVM_DEPRECATED_MAIN_0x07 _IO(KVMIO, 0x07)
-#define __KVM_DEPRECATED_MAIN_0x08 _IO(KVMIO, 0x08)
-
-#define __KVM_DEPRECATED_VM_R_0x70 _IOR(KVMIO, 0x70, struct kvm_assigned_irq)
-
-struct kvm_breakpoint {
- __u32 enabled;
- __u32 padding;
- __u64 address;
-};
-
-struct kvm_debug_guest {
- __u32 enabled;
- __u32 pad;
- struct kvm_breakpoint breakpoints[4];
- __u32 singlestep;
-};
-
-#define __KVM_DEPRECATED_VCPU_W_0x87 _IOW(KVMIO, 0x87, struct kvm_debug_guest)
-
-/* *** End of deprecated interfaces *** */
-
-
/* for KVM_SET_USER_MEMORY_REGION */
struct kvm_userspace_memory_region {
__u32 slot;
@@ -95,6 +25,19 @@
__u64 userspace_addr; /* start of the userspace allocated memory */
};
+/* for KVM_SET_USER_MEMORY_REGION2 */
+struct kvm_userspace_memory_region2 {
+ __u32 slot;
+ __u32 flags;
+ __u64 guest_phys_addr;
+ __u64 memory_size;
+ __u64 userspace_addr;
+ __u64 guest_memfd_offset;
+ __u32 guest_memfd;
+ __u32 pad1;
+ __u64 pad2[14];
+};
+
/*
* The bit 0 ~ bit 15 of kvm_userspace_memory_region::flags are visible for
* userspace, other bits are reserved for kvm internal use which are defined
@@ -102,6 +45,7 @@
*/
#define KVM_MEM_LOG_DIRTY_PAGES (1UL << 0)
#define KVM_MEM_READONLY (1UL << 1)
+#define KVM_MEM_GUEST_MEMFD (1UL << 2)
/* for KVM_IRQ_LINE */
struct kvm_irq_level {
@@ -265,6 +209,7 @@
#define KVM_EXIT_RISCV_CSR 36
#define KVM_EXIT_NOTIFY 37
#define KVM_EXIT_LOONGARCH_IOCSR 38
+#define KVM_EXIT_MEMORY_FAULT 39
/* For KVM_EXIT_INTERNAL_ERROR */
/* Emulate instruction failed. */
@@ -514,6 +459,13 @@
#define KVM_NOTIFY_CONTEXT_INVALID (1 << 0)
__u32 flags;
} notify;
+ /* KVM_EXIT_MEMORY_FAULT */
+ struct {
+#define KVM_MEMORY_EXIT_FLAG_PRIVATE (1ULL << 3)
+ __u64 flags;
+ __u64 gpa;
+ __u64 size;
+ } memory_fault;
/* Fix the size of the union. */
char padding[256];
};
@@ -941,9 +893,6 @@
*/
#define KVM_GET_VCPU_MMAP_SIZE _IO(KVMIO, 0x04) /* in bytes */
#define KVM_GET_SUPPORTED_CPUID _IOWR(KVMIO, 0x05, struct kvm_cpuid2)
-#define KVM_TRACE_ENABLE __KVM_DEPRECATED_MAIN_W_0x06
-#define KVM_TRACE_PAUSE __KVM_DEPRECATED_MAIN_0x07
-#define KVM_TRACE_DISABLE __KVM_DEPRECATED_MAIN_0x08
#define KVM_GET_EMULATED_CPUID _IOWR(KVMIO, 0x09, struct kvm_cpuid2)
#define KVM_GET_MSR_FEATURE_INDEX_LIST _IOWR(KVMIO, 0x0a, struct kvm_msr_list)
@@ -1197,6 +1146,11 @@
#define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228
#define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229
#define KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES 230
+#define KVM_CAP_USER_MEMORY2 231
+#define KVM_CAP_MEMORY_FAULT_INFO 232
+#define KVM_CAP_MEMORY_ATTRIBUTES 233
+#define KVM_CAP_GUEST_MEMFD 234
+#define KVM_CAP_VM_TYPES 235
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1287,6 +1241,7 @@
#define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL (1 << 4)
#define KVM_XEN_HVM_CONFIG_EVTCHN_SEND (1 << 5)
#define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG (1 << 6)
+#define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE (1 << 7)
struct kvm_xen_hvm_config {
__u32 flags;
@@ -1479,6 +1434,8 @@
struct kvm_userspace_memory_region)
#define KVM_SET_TSS_ADDR _IO(KVMIO, 0x47)
#define KVM_SET_IDENTITY_MAP_ADDR _IOW(KVMIO, 0x48, __u64)
+#define KVM_SET_USER_MEMORY_REGION2 _IOW(KVMIO, 0x49, \
+ struct kvm_userspace_memory_region2)
/* enable ucontrol for s390 */
struct kvm_s390_ucas_mapping {
@@ -1503,20 +1460,8 @@
_IOW(KVMIO, 0x67, struct kvm_coalesced_mmio_zone)
#define KVM_UNREGISTER_COALESCED_MMIO \
_IOW(KVMIO, 0x68, struct kvm_coalesced_mmio_zone)
-#define KVM_ASSIGN_PCI_DEVICE _IOR(KVMIO, 0x69, \
- struct kvm_assigned_pci_dev)
#define KVM_SET_GSI_ROUTING _IOW(KVMIO, 0x6a, struct kvm_irq_routing)
-/* deprecated, replaced by KVM_ASSIGN_DEV_IRQ */
-#define KVM_ASSIGN_IRQ __KVM_DEPRECATED_VM_R_0x70
-#define KVM_ASSIGN_DEV_IRQ _IOW(KVMIO, 0x70, struct kvm_assigned_irq)
#define KVM_REINJECT_CONTROL _IO(KVMIO, 0x71)
-#define KVM_DEASSIGN_PCI_DEVICE _IOW(KVMIO, 0x72, \
- struct kvm_assigned_pci_dev)
-#define KVM_ASSIGN_SET_MSIX_NR _IOW(KVMIO, 0x73, \
- struct kvm_assigned_msix_nr)
-#define KVM_ASSIGN_SET_MSIX_ENTRY _IOW(KVMIO, 0x74, \
- struct kvm_assigned_msix_entry)
-#define KVM_DEASSIGN_DEV_IRQ _IOW(KVMIO, 0x75, struct kvm_assigned_irq)
#define KVM_IRQFD _IOW(KVMIO, 0x76, struct kvm_irqfd)
#define KVM_CREATE_PIT2 _IOW(KVMIO, 0x77, struct kvm_pit_config)
#define KVM_SET_BOOT_CPU_ID _IO(KVMIO, 0x78)
@@ -1533,9 +1478,6 @@
* KVM_CAP_VM_TSC_CONTROL to set defaults for a VM */
#define KVM_SET_TSC_KHZ _IO(KVMIO, 0xa2)
#define KVM_GET_TSC_KHZ _IO(KVMIO, 0xa3)
-/* Available with KVM_CAP_PCI_2_3 */
-#define KVM_ASSIGN_SET_INTX_MASK _IOW(KVMIO, 0xa4, \
- struct kvm_assigned_pci_dev)
/* Available with KVM_CAP_SIGNAL_MSI */
#define KVM_SIGNAL_MSI _IOW(KVMIO, 0xa5, struct kvm_msi)
/* Available with KVM_CAP_PPC_GET_SMMU_INFO */
@@ -1588,8 +1530,6 @@
#define KVM_SET_SREGS _IOW(KVMIO, 0x84, struct kvm_sregs)
#define KVM_TRANSLATE _IOWR(KVMIO, 0x85, struct kvm_translation)
#define KVM_INTERRUPT _IOW(KVMIO, 0x86, struct kvm_interrupt)
-/* KVM_DEBUG_GUEST is no longer supported, use KVM_SET_GUEST_DEBUG instead */
-#define KVM_DEBUG_GUEST __KVM_DEPRECATED_VCPU_W_0x87
#define KVM_GET_MSRS _IOWR(KVMIO, 0x88, struct kvm_msrs)
#define KVM_SET_MSRS _IOW(KVMIO, 0x89, struct kvm_msrs)
#define KVM_SET_CPUID _IOW(KVMIO, 0x8a, struct kvm_cpuid)
@@ -2263,4 +2203,24 @@
/* flags for kvm_s390_zpci_op->u.reg_aen.flags */
#define KVM_S390_ZPCIOP_REGAEN_HOST (1 << 0)
+/* Available with KVM_CAP_MEMORY_ATTRIBUTES */
+#define KVM_SET_MEMORY_ATTRIBUTES _IOW(KVMIO, 0xd2, struct kvm_memory_attributes)
+
+struct kvm_memory_attributes {
+ __u64 address;
+ __u64 size;
+ __u64 attributes;
+ __u64 flags;
+};
+
+#define KVM_MEMORY_ATTRIBUTE_PRIVATE (1ULL << 3)
+
+#define KVM_CREATE_GUEST_MEMFD _IOWR(KVMIO, 0xd4, struct kvm_create_guest_memfd)
+
+struct kvm_create_guest_memfd {
+ __u64 size;
+ __u64 flags;
+ __u64 reserved[6];
+};
+
#endif /* __LINUX_KVM_H */
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
index 953c75f..4283de2 100644
--- a/linux-headers/linux/userfaultfd.h
+++ b/linux-headers/linux/userfaultfd.h
@@ -41,7 +41,8 @@
UFFD_FEATURE_WP_HUGETLBFS_SHMEM | \
UFFD_FEATURE_WP_UNPOPULATED | \
UFFD_FEATURE_POISON | \
- UFFD_FEATURE_WP_ASYNC)
+ UFFD_FEATURE_WP_ASYNC | \
+ UFFD_FEATURE_MOVE)
#define UFFD_API_IOCTLS \
((__u64)1 << _UFFDIO_REGISTER | \
(__u64)1 << _UFFDIO_UNREGISTER | \
@@ -50,6 +51,7 @@
((__u64)1 << _UFFDIO_WAKE | \
(__u64)1 << _UFFDIO_COPY | \
(__u64)1 << _UFFDIO_ZEROPAGE | \
+ (__u64)1 << _UFFDIO_MOVE | \
(__u64)1 << _UFFDIO_WRITEPROTECT | \
(__u64)1 << _UFFDIO_CONTINUE | \
(__u64)1 << _UFFDIO_POISON)
@@ -73,6 +75,7 @@
#define _UFFDIO_WAKE (0x02)
#define _UFFDIO_COPY (0x03)
#define _UFFDIO_ZEROPAGE (0x04)
+#define _UFFDIO_MOVE (0x05)
#define _UFFDIO_WRITEPROTECT (0x06)
#define _UFFDIO_CONTINUE (0x07)
#define _UFFDIO_POISON (0x08)
@@ -92,6 +95,8 @@
struct uffdio_copy)
#define UFFDIO_ZEROPAGE _IOWR(UFFDIO, _UFFDIO_ZEROPAGE, \
struct uffdio_zeropage)
+#define UFFDIO_MOVE _IOWR(UFFDIO, _UFFDIO_MOVE, \
+ struct uffdio_move)
#define UFFDIO_WRITEPROTECT _IOWR(UFFDIO, _UFFDIO_WRITEPROTECT, \
struct uffdio_writeprotect)
#define UFFDIO_CONTINUE _IOWR(UFFDIO, _UFFDIO_CONTINUE, \
@@ -222,6 +227,9 @@
* asynchronous mode is supported in which the write fault is
* automatically resolved and write-protection is un-set.
* It implies UFFD_FEATURE_WP_UNPOPULATED.
+ *
+ * UFFD_FEATURE_MOVE indicates that the kernel supports moving an
+ * existing page contents from userspace.
*/
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP (1<<0)
#define UFFD_FEATURE_EVENT_FORK (1<<1)
@@ -239,6 +247,7 @@
#define UFFD_FEATURE_WP_UNPOPULATED (1<<13)
#define UFFD_FEATURE_POISON (1<<14)
#define UFFD_FEATURE_WP_ASYNC (1<<15)
+#define UFFD_FEATURE_MOVE (1<<16)
__u64 features;
__u64 ioctls;
@@ -347,6 +356,24 @@
__s64 updated;
};
+struct uffdio_move {
+ __u64 dst;
+ __u64 src;
+ __u64 len;
+ /*
+ * Especially if used to atomically remove memory from the
+ * address space the wake on the dst range is not needed.
+ */
+#define UFFDIO_MOVE_MODE_DONTWAKE ((__u64)1<<0)
+#define UFFDIO_MOVE_MODE_ALLOW_SRC_HOLES ((__u64)1<<1)
+ __u64 mode;
+ /*
+ * "move" is written by the ioctl and must be at the end: the
+ * copy_from_user will not read the last 8 bytes.
+ */
+ __s64 move;
+};
+
/*
* Flags for the userfaultfd(2) system call itself.
*/
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
index 8e175ece3..b4be37b 100644
--- a/linux-headers/linux/vfio.h
+++ b/linux-headers/linux/vfio.h
@@ -1219,6 +1219,7 @@
VFIO_DEVICE_STATE_RUNNING_P2P = 5,
VFIO_DEVICE_STATE_PRE_COPY = 6,
VFIO_DEVICE_STATE_PRE_COPY_P2P = 7,
+ VFIO_DEVICE_STATE_NR,
};
/**
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 7f30def..597bdf0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8808,13 +8808,43 @@
#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
-#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
-#define RISCV_HWPROBE_IMA_FD (1 << 0)
-#define RISCV_HWPROBE_IMA_C (1 << 1)
-#define RISCV_HWPROBE_IMA_V (1 << 2)
-#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
-#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
-#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
+#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
+#define RISCV_HWPROBE_IMA_FD (1 << 0)
+#define RISCV_HWPROBE_IMA_C (1 << 1)
+#define RISCV_HWPROBE_IMA_V (1 << 2)
+#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
+#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
+#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
+#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
+#define RISCV_HWPROBE_EXT_ZBC (1 << 7)
+#define RISCV_HWPROBE_EXT_ZBKB (1 << 8)
+#define RISCV_HWPROBE_EXT_ZBKC (1 << 9)
+#define RISCV_HWPROBE_EXT_ZBKX (1 << 10)
+#define RISCV_HWPROBE_EXT_ZKND (1 << 11)
+#define RISCV_HWPROBE_EXT_ZKNE (1 << 12)
+#define RISCV_HWPROBE_EXT_ZKNH (1 << 13)
+#define RISCV_HWPROBE_EXT_ZKSED (1 << 14)
+#define RISCV_HWPROBE_EXT_ZKSH (1 << 15)
+#define RISCV_HWPROBE_EXT_ZKT (1 << 16)
+#define RISCV_HWPROBE_EXT_ZVBB (1 << 17)
+#define RISCV_HWPROBE_EXT_ZVBC (1 << 18)
+#define RISCV_HWPROBE_EXT_ZVKB (1 << 19)
+#define RISCV_HWPROBE_EXT_ZVKG (1 << 20)
+#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21)
+#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22)
+#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23)
+#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
+#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
+#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
+#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
+#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
+#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
+#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
+#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
+#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
+#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
+#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
@@ -8873,6 +8903,66 @@
RISCV_HWPROBE_EXT_ZBB : 0;
value |= cfg->ext_zbs ?
RISCV_HWPROBE_EXT_ZBS : 0;
+ value |= cfg->ext_zicboz ?
+ RISCV_HWPROBE_EXT_ZICBOZ : 0;
+ value |= cfg->ext_zbc ?
+ RISCV_HWPROBE_EXT_ZBC : 0;
+ value |= cfg->ext_zbkb ?
+ RISCV_HWPROBE_EXT_ZBKB : 0;
+ value |= cfg->ext_zbkc ?
+ RISCV_HWPROBE_EXT_ZBKC : 0;
+ value |= cfg->ext_zbkx ?
+ RISCV_HWPROBE_EXT_ZBKX : 0;
+ value |= cfg->ext_zknd ?
+ RISCV_HWPROBE_EXT_ZKND : 0;
+ value |= cfg->ext_zkne ?
+ RISCV_HWPROBE_EXT_ZKNE : 0;
+ value |= cfg->ext_zknh ?
+ RISCV_HWPROBE_EXT_ZKNH : 0;
+ value |= cfg->ext_zksed ?
+ RISCV_HWPROBE_EXT_ZKSED : 0;
+ value |= cfg->ext_zksh ?
+ RISCV_HWPROBE_EXT_ZKSH : 0;
+ value |= cfg->ext_zkt ?
+ RISCV_HWPROBE_EXT_ZKT : 0;
+ value |= cfg->ext_zvbb ?
+ RISCV_HWPROBE_EXT_ZVBB : 0;
+ value |= cfg->ext_zvbc ?
+ RISCV_HWPROBE_EXT_ZVBC : 0;
+ value |= cfg->ext_zvkb ?
+ RISCV_HWPROBE_EXT_ZVKB : 0;
+ value |= cfg->ext_zvkg ?
+ RISCV_HWPROBE_EXT_ZVKG : 0;
+ value |= cfg->ext_zvkned ?
+ RISCV_HWPROBE_EXT_ZVKNED : 0;
+ value |= cfg->ext_zvknha ?
+ RISCV_HWPROBE_EXT_ZVKNHA : 0;
+ value |= cfg->ext_zvknhb ?
+ RISCV_HWPROBE_EXT_ZVKNHB : 0;
+ value |= cfg->ext_zvksed ?
+ RISCV_HWPROBE_EXT_ZVKSED : 0;
+ value |= cfg->ext_zvksh ?
+ RISCV_HWPROBE_EXT_ZVKSH : 0;
+ value |= cfg->ext_zvkt ?
+ RISCV_HWPROBE_EXT_ZVKT : 0;
+ value |= cfg->ext_zfh ?
+ RISCV_HWPROBE_EXT_ZFH : 0;
+ value |= cfg->ext_zfhmin ?
+ RISCV_HWPROBE_EXT_ZFHMIN : 0;
+ value |= cfg->ext_zihintntl ?
+ RISCV_HWPROBE_EXT_ZIHINTNTL : 0;
+ value |= cfg->ext_zvfh ?
+ RISCV_HWPROBE_EXT_ZVFH : 0;
+ value |= cfg->ext_zvfhmin ?
+ RISCV_HWPROBE_EXT_ZVFHMIN : 0;
+ value |= cfg->ext_zfa ?
+ RISCV_HWPROBE_EXT_ZFA : 0;
+ value |= cfg->ext_ztso ?
+ RISCV_HWPROBE_EXT_ZTSO : 0;
+ value |= cfg->ext_zacas ?
+ RISCV_HWPROBE_EXT_ZACAS : 0;
+ value |= cfg->ext_zicond ?
+ RISCV_HWPROBE_EXT_ZICOND : 0;
__put_user(value, &pair->value);
break;
case RISCV_HWPROBE_KEY_CPUPERF_0:
diff --git a/qapi/ui.json b/qapi/ui.json
index 1726f15..5744c24 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@ -1421,6 +1421,9 @@
# turned off the host window will be resized instead. Defaults to
# "off". (Since 8.2)
#
+# @zoom-interpolation: Apply interpolation to smooth output when
+# zoom-to-fit is enabled. Defaults to "off". (Since 9.0)
+#
# Since: 7.0
##
{ 'struct': 'DisplayCocoa',
@@ -1428,7 +1431,8 @@
'*left-command-key': 'bool',
'*full-grab': 'bool',
'*swap-opt-cmd': 'bool',
- '*zoom-to-fit': 'bool'
+ '*zoom-to-fit': 'bool',
+ '*zoom-interpolation': 'bool'
} }
##
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 7567854..e5758d9 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -741,6 +741,16 @@
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
}
+static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
+}
+
+static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
+}
+
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a5b3d8f..bc0c848 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -140,11 +140,6 @@
uint64_t ctl; /* Timer Control register */
} ARMGenericTimer;
-#define VTCR_NSW (1u << 29)
-#define VTCR_NSA (1u << 30)
-#define VSTCR_SW VTCR_NSW
-#define VSTCR_SA VTCR_NSA
-
/* Define a maximum sized vector register.
* For 32-bit, this is a 128-bit NEON/AdvSIMD register.
* For 64-bit, this is a 2048-bit SVE register.
@@ -457,6 +452,7 @@
uint64_t c14_cntkctl; /* Timer Control register */
uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
+ uint64_t cntpoff_el2; /* Counter Physical Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
uint32_t c15_ticonfig; /* TI925T configuration byte. */
@@ -1375,73 +1371,6 @@
#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
-/* Bit definitions for CPACR (AArch32 only) */
-FIELD(CPACR, CP10, 20, 2)
-FIELD(CPACR, CP11, 22, 2)
-FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
-FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
-FIELD(CPACR, ASEDIS, 31, 1)
-
-/* Bit definitions for CPACR_EL1 (AArch64 only) */
-FIELD(CPACR_EL1, ZEN, 16, 2)
-FIELD(CPACR_EL1, FPEN, 20, 2)
-FIELD(CPACR_EL1, SMEN, 24, 2)
-FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
-
-/* Bit definitions for HCPTR (AArch32 only) */
-FIELD(HCPTR, TCP10, 10, 1)
-FIELD(HCPTR, TCP11, 11, 1)
-FIELD(HCPTR, TASE, 15, 1)
-FIELD(HCPTR, TTA, 20, 1)
-FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
-FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
-
-/* Bit definitions for CPTR_EL2 (AArch64 only) */
-FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
-FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
-FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
-FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
-FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
-FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
-FIELD(CPTR_EL2, TTA, 28, 1)
-FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
-FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
-
-/* Bit definitions for CPTR_EL3 (AArch64 only) */
-FIELD(CPTR_EL3, EZ, 8, 1)
-FIELD(CPTR_EL3, TFP, 10, 1)
-FIELD(CPTR_EL3, ESM, 12, 1)
-FIELD(CPTR_EL3, TTA, 20, 1)
-FIELD(CPTR_EL3, TAM, 30, 1)
-FIELD(CPTR_EL3, TCPAC, 31, 1)
-
-#define MDCR_MTPME (1U << 28)
-#define MDCR_TDCC (1U << 27)
-#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
-#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
-#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
-#define MDCR_EPMAD (1U << 21)
-#define MDCR_EDAD (1U << 20)
-#define MDCR_TTRF (1U << 19)
-#define MDCR_STE (1U << 18) /* MDCR_EL3 */
-#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
-#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
-#define MDCR_SDD (1U << 16)
-#define MDCR_SPD (3U << 14)
-#define MDCR_TDRA (1U << 11)
-#define MDCR_TDOSA (1U << 10)
-#define MDCR_TDA (1U << 9)
-#define MDCR_TDE (1U << 8)
-#define MDCR_HPME (1U << 7)
-#define MDCR_TPM (1U << 6)
-#define MDCR_TPMCR (1U << 5)
-#define MDCR_HPMN (0x1fU)
-
-/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
-#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
- MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
- MDCR_STE | MDCR_SPME | MDCR_SPD)
-
#define CPSR_M (0x1fU)
#define CPSR_T (1U << 5)
#define CPSR_F (1U << 6)
@@ -1488,41 +1417,6 @@
#define XPSR_NZCV CPSR_NZCV
#define XPSR_IT CPSR_IT
-#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
-#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
-#define TTBCR_PD0 (1U << 4)
-#define TTBCR_PD1 (1U << 5)
-#define TTBCR_EPD0 (1U << 7)
-#define TTBCR_IRGN0 (3U << 8)
-#define TTBCR_ORGN0 (3U << 10)
-#define TTBCR_SH0 (3U << 12)
-#define TTBCR_T1SZ (3U << 16)
-#define TTBCR_A1 (1U << 22)
-#define TTBCR_EPD1 (1U << 23)
-#define TTBCR_IRGN1 (3U << 24)
-#define TTBCR_ORGN1 (3U << 26)
-#define TTBCR_SH1 (1U << 28)
-#define TTBCR_EAE (1U << 31)
-
-FIELD(VTCR, T0SZ, 0, 6)
-FIELD(VTCR, SL0, 6, 2)
-FIELD(VTCR, IRGN0, 8, 2)
-FIELD(VTCR, ORGN0, 10, 2)
-FIELD(VTCR, SH0, 12, 2)
-FIELD(VTCR, TG0, 14, 2)
-FIELD(VTCR, PS, 16, 3)
-FIELD(VTCR, VS, 19, 1)
-FIELD(VTCR, HA, 21, 1)
-FIELD(VTCR, HD, 22, 1)
-FIELD(VTCR, HWU59, 25, 1)
-FIELD(VTCR, HWU60, 26, 1)
-FIELD(VTCR, HWU61, 27, 1)
-FIELD(VTCR, HWU62, 28, 1)
-FIELD(VTCR, NSW, 29, 1)
-FIELD(VTCR, NSA, 30, 1)
-FIELD(VTCR, DS, 32, 1)
-FIELD(VTCR, SL2, 33, 1)
-
/* Bit definitions for ARMv8 SPSR (PSTATE) format.
* Only these are valid when in AArch64 mode; in
* AArch32 mode SPSRs are basically CPSR-format.
@@ -1730,21 +1624,6 @@
#define HCR_TWEDEN (1ULL << 59)
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
-#define HCRX_ENAS0 (1ULL << 0)
-#define HCRX_ENALS (1ULL << 1)
-#define HCRX_ENASR (1ULL << 2)
-#define HCRX_FNXS (1ULL << 3)
-#define HCRX_FGTNXS (1ULL << 4)
-#define HCRX_SMPME (1ULL << 5)
-#define HCRX_TALLINT (1ULL << 6)
-#define HCRX_VINMI (1ULL << 7)
-#define HCRX_VFNMI (1ULL << 8)
-#define HCRX_CMOW (1ULL << 9)
-#define HCRX_MCE2 (1ULL << 10)
-#define HCRX_MSCEN (1ULL << 11)
-
-#define HPFAR_NS (1ULL << 63)
-
#define SCR_NS (1ULL << 0)
#define SCR_IRQ (1ULL << 1)
#define SCR_FIQ (1ULL << 2)
@@ -1783,12 +1662,6 @@
#define SCR_GPF (1ULL << 48)
#define SCR_NSE (1ULL << 62)
-#define HSTR_TTEE (1 << 16)
-#define HSTR_TJDBX (1 << 17)
-
-#define CNTHCTL_CNTVMASK (1 << 18)
-#define CNTHCTL_CNTPMASK (1 << 19)
-
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 90c4fb7..3f3a5b5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1923,6 +1923,9 @@
if (cpu_isar_feature(aa64_rme, cpu)) {
valid_mask |= SCR_NSE | SCR_GPF;
}
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
+ valid_mask |= SCR_ECVEN;
+ }
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -2530,6 +2533,11 @@
: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
return CP_ACCESS_TRAP_EL2;
}
+ if (has_el2 && timeridx == GTIMER_VIRT) {
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
break;
}
return CP_ACCESS_OK;
@@ -2573,6 +2581,11 @@
}
}
}
+ if (has_el2 && timeridx == GTIMER_VIRT) {
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
break;
}
return CP_ACCESS_OK;
@@ -2652,8 +2665,8 @@
* It is RES0 in Secure and NonSecure state.
*/
if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&
- ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||
- (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {
+ ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||
+ (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {
irqstate = 0;
}
@@ -2672,6 +2685,25 @@
gt_update_irq(cpu, GTIMER_PHYS);
}
+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
+{
+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&
+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
+ arm_is_el2_enabled(env) &&
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
+ return env->cp15.cntpoff_el2;
+ }
+ return 0;
+}
+
+static uint64_t gt_phys_cnt_offset(CPUARMState *env)
+{
+ if (arm_current_el(env) >= 2) {
+ return 0;
+ }
+ return gt_phys_raw_cnt_offset(env);
+}
+
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
{
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
@@ -2682,7 +2714,7 @@
* reset timer to when ISTATUS next has to change
*/
uint64_t offset = timeridx == GTIMER_VIRT ?
- cpu->env.cp15.cntvoff_el2 : 0;
+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
uint64_t count = gt_get_countervalue(&cpu->env);
/* Note that this must be unsigned 64 bit arithmetic: */
int istatus = count - offset >= gt->cval;
@@ -2745,7 +2777,7 @@
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- return gt_get_countervalue(env);
+ return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
}
static uint64_t gt_virt_cnt_offset(CPUARMState *env)
@@ -2794,6 +2826,9 @@
case GTIMER_HYPVIRT:
offset = gt_virt_cnt_offset(env);
break;
+ case GTIMER_PHYS:
+ offset = gt_phys_cnt_offset(env);
+ break;
}
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
@@ -2811,6 +2846,9 @@
case GTIMER_HYPVIRT:
offset = gt_virt_cnt_offset(env);
break;
+ case GTIMER_PHYS:
+ offset = gt_phys_cnt_offset(env);
+ break;
}
trace_arm_gt_tval_write(timeridx, value);
@@ -2968,12 +3006,40 @@
{
ARMCPU *cpu = env_archcpu(env);
uint32_t oldval = env->cp15.cnthctl_el2;
+ uint32_t valid_mask =
+ R_CNTHCTL_EL0PCTEN_E2H1_MASK |
+ R_CNTHCTL_EL0VCTEN_E2H1_MASK |
+ R_CNTHCTL_EVNTEN_MASK |
+ R_CNTHCTL_EVNTDIR_MASK |
+ R_CNTHCTL_EVNTI_MASK |
+ R_CNTHCTL_EL0VTEN_MASK |
+ R_CNTHCTL_EL0PTEN_MASK |
+ R_CNTHCTL_EL1PCTEN_E2H1_MASK |
+ R_CNTHCTL_EL1PTEN_MASK;
+
+ if (cpu_isar_feature(aa64_rme, cpu)) {
+ valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
+ }
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
+ valid_mask |=
+ R_CNTHCTL_EL1TVT_MASK |
+ R_CNTHCTL_EL1TVCT_MASK |
+ R_CNTHCTL_EL1NVPCT_MASK |
+ R_CNTHCTL_EL1NVVCT_MASK |
+ R_CNTHCTL_EVNTIS_MASK;
+ }
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
+ valid_mask |= R_CNTHCTL_ECV_MASK;
+ }
+
+ /* Clear RES0 bits */
+ value &= valid_mask;
raw_write(env, ri, value);
- if ((oldval ^ value) & CNTHCTL_CNTVMASK) {
+ if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
gt_update_irq(cpu, GTIMER_VIRT);
- } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {
+ } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {
gt_update_irq(cpu, GTIMER_PHYS);
}
}
@@ -3354,6 +3420,62 @@
},
};
+/*
+ * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
+ * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
+ * so our implementations here are identical to the normal registers.
+ */
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
+ { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9,
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
+ .accessfn = gt_vct_access,
+ .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
+ },
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
+ },
+ { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8,
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
+ .accessfn = gt_pct_access,
+ .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
+ },
+ { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5,
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
+ },
+};
+
+static CPAccessResult gt_cntpoff_access(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {
+ return CP_ACCESS_TRAP_EL3;
+ }
+ return CP_ACCESS_OK;
+}
+
+static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ trace_arm_gt_cntpoff_write(value);
+ raw_write(env, ri, value);
+ gt_recalc_timer(cpu, GTIMER_PHYS);
+}
+
+static const ARMCPRegInfo gen_timer_cntpoff_reginfo = {
+ .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,
+ .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
+ .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write,
+ .nv2_redirect_offset = 0x1a8,
+ .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2),
+};
#else
/*
@@ -3387,6 +3509,18 @@
},
};
+/*
+ * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
+ * is exposed to userspace by Linux.
+ */
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
+ .readfn = gt_virt_cnt_read,
+ },
+};
+
#endif
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -6547,15 +6681,38 @@
{
if (arm_current_el(env) == 1) {
/* This must be a FEAT_NV access */
- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
return CP_ACCESS_OK;
}
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
}
return CP_ACCESS_OK;
}
+static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 1) {
+ /* This must be a FEAT_NV access with NVx == 101 */
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ return e2h_access(env, ri, isread);
+}
+
+static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 1) {
+ /* This must be a FEAT_NV access with NVx == 101 */
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ return e2h_access(env, ri, isread);
+}
+
/* Test if system register redirection is to occur in the current state. */
static bool redirect_for_e2h(CPUARMState *env)
{
@@ -8381,14 +8538,14 @@
{ .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
.type = ARM_CP_IO | ARM_CP_ALIAS,
- .access = PL2_RW, .accessfn = e2h_access,
+ .access = PL2_RW, .accessfn = access_el1nvpct,
.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
.type = ARM_CP_IO | ARM_CP_ALIAS,
- .access = PL2_RW, .accessfn = e2h_access,
+ .access = PL2_RW, .accessfn = access_el1nvvct,
.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
@@ -8407,14 +8564,14 @@
.type = ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,
- .access = PL2_RW, .accessfn = e2h_access,
+ .access = PL2_RW, .accessfn = access_el1nvpct,
.writefn = gt_phys_cval_write, .raw_writefn = raw_write },
{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
.type = ARM_CP_IO | ARM_CP_ALIAS,
.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
- .access = PL2_RW, .accessfn = e2h_access,
+ .access = PL2_RW, .accessfn = access_el1nvvct,
.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
#endif
};
@@ -9200,6 +9357,14 @@
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
}
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
+ define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
+ }
+#ifndef CONFIG_USER_ONLY
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
+ define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo);
+ }
+#endif
if (arm_feature(env, ARM_FEATURE_VAPA)) {
ARMCPRegInfo vapa_cp_reginfo[] = {
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 860bcc0..dd3da21 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -99,6 +99,157 @@
FIELD(DBGWCR, MASK, 24, 5)
FIELD(DBGWCR, SSCE, 29, 1)
+#define VTCR_NSW (1u << 29)
+#define VTCR_NSA (1u << 30)
+#define VSTCR_SW VTCR_NSW
+#define VSTCR_SA VTCR_NSA
+
+/* Bit definitions for CPACR (AArch32 only) */
+FIELD(CPACR, CP10, 20, 2)
+FIELD(CPACR, CP11, 22, 2)
+FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
+FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
+FIELD(CPACR, ASEDIS, 31, 1)
+
+/* Bit definitions for CPACR_EL1 (AArch64 only) */
+FIELD(CPACR_EL1, ZEN, 16, 2)
+FIELD(CPACR_EL1, FPEN, 20, 2)
+FIELD(CPACR_EL1, SMEN, 24, 2)
+FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
+
+/* Bit definitions for HCPTR (AArch32 only) */
+FIELD(HCPTR, TCP10, 10, 1)
+FIELD(HCPTR, TCP11, 11, 1)
+FIELD(HCPTR, TASE, 15, 1)
+FIELD(HCPTR, TTA, 20, 1)
+FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
+FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
+
+/* Bit definitions for CPTR_EL2 (AArch64 only) */
+FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
+FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
+FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
+FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
+FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
+FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
+FIELD(CPTR_EL2, TTA, 28, 1)
+FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
+FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
+
+/* Bit definitions for CPTR_EL3 (AArch64 only) */
+FIELD(CPTR_EL3, EZ, 8, 1)
+FIELD(CPTR_EL3, TFP, 10, 1)
+FIELD(CPTR_EL3, ESM, 12, 1)
+FIELD(CPTR_EL3, TTA, 20, 1)
+FIELD(CPTR_EL3, TAM, 30, 1)
+FIELD(CPTR_EL3, TCPAC, 31, 1)
+
+#define MDCR_MTPME (1U << 28)
+#define MDCR_TDCC (1U << 27)
+#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
+#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
+#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
+#define MDCR_EPMAD (1U << 21)
+#define MDCR_EDAD (1U << 20)
+#define MDCR_TTRF (1U << 19)
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
+#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
+#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
+#define MDCR_SDD (1U << 16)
+#define MDCR_SPD (3U << 14)
+#define MDCR_TDRA (1U << 11)
+#define MDCR_TDOSA (1U << 10)
+#define MDCR_TDA (1U << 9)
+#define MDCR_TDE (1U << 8)
+#define MDCR_HPME (1U << 7)
+#define MDCR_TPM (1U << 6)
+#define MDCR_TPMCR (1U << 5)
+#define MDCR_HPMN (0x1fU)
+
+/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
+
+#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
+#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
+#define TTBCR_PD0 (1U << 4)
+#define TTBCR_PD1 (1U << 5)
+#define TTBCR_EPD0 (1U << 7)
+#define TTBCR_IRGN0 (3U << 8)
+#define TTBCR_ORGN0 (3U << 10)
+#define TTBCR_SH0 (3U << 12)
+#define TTBCR_T1SZ (3U << 16)
+#define TTBCR_A1 (1U << 22)
+#define TTBCR_EPD1 (1U << 23)
+#define TTBCR_IRGN1 (3U << 24)
+#define TTBCR_ORGN1 (3U << 26)
+#define TTBCR_SH1 (1U << 28)
+#define TTBCR_EAE (1U << 31)
+
+FIELD(VTCR, T0SZ, 0, 6)
+FIELD(VTCR, SL0, 6, 2)
+FIELD(VTCR, IRGN0, 8, 2)
+FIELD(VTCR, ORGN0, 10, 2)
+FIELD(VTCR, SH0, 12, 2)
+FIELD(VTCR, TG0, 14, 2)
+FIELD(VTCR, PS, 16, 3)
+FIELD(VTCR, VS, 19, 1)
+FIELD(VTCR, HA, 21, 1)
+FIELD(VTCR, HD, 22, 1)
+FIELD(VTCR, HWU59, 25, 1)
+FIELD(VTCR, HWU60, 26, 1)
+FIELD(VTCR, HWU61, 27, 1)
+FIELD(VTCR, HWU62, 28, 1)
+FIELD(VTCR, NSW, 29, 1)
+FIELD(VTCR, NSA, 30, 1)
+FIELD(VTCR, DS, 32, 1)
+FIELD(VTCR, SL2, 33, 1)
+
+#define HCRX_ENAS0 (1ULL << 0)
+#define HCRX_ENALS (1ULL << 1)
+#define HCRX_ENASR (1ULL << 2)
+#define HCRX_FNXS (1ULL << 3)
+#define HCRX_FGTNXS (1ULL << 4)
+#define HCRX_SMPME (1ULL << 5)
+#define HCRX_TALLINT (1ULL << 6)
+#define HCRX_VINMI (1ULL << 7)
+#define HCRX_VFNMI (1ULL << 8)
+#define HCRX_CMOW (1ULL << 9)
+#define HCRX_MCE2 (1ULL << 10)
+#define HCRX_MSCEN (1ULL << 11)
+
+#define HPFAR_NS (1ULL << 63)
+
+#define HSTR_TTEE (1 << 16)
+#define HSTR_TJDBX (1 << 17)
+
+/*
+ * Depending on the value of HCR_EL2.E2H, bits 0 and 1
+ * have different bit definitions, and EL1PCTEN might be
+ * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to
+ * disambiguate if necessary.
+ */
+FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)
+FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)
+FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)
+FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)
+FIELD(CNTHCTL, EVNTEN, 2, 1)
+FIELD(CNTHCTL, EVNTDIR, 3, 1)
+FIELD(CNTHCTL, EVNTI, 4, 4)
+FIELD(CNTHCTL, EL0VTEN, 8, 1)
+FIELD(CNTHCTL, EL0PTEN, 9, 1)
+FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)
+FIELD(CNTHCTL, EL1PTEN, 11, 1)
+FIELD(CNTHCTL, ECV, 12, 1)
+FIELD(CNTHCTL, EL1TVT, 13, 1)
+FIELD(CNTHCTL, EL1TVCT, 14, 1)
+FIELD(CNTHCTL, EL1NVPCT, 15, 1)
+FIELD(CNTHCTL, EL1NVVCT, 16, 1)
+FIELD(CNTHCTL, EVNTIS, 17, 1)
+FIELD(CNTHCTL, CNTVMASK, 18, 1)
+FIELD(CNTHCTL, CNTPMASK, 19, 1)
+
/* We use a few fake FSR values for internal purposes in M profile.
* M profile cores don't have A/R format FSRs, but currently our
* get_phys_addr() code assumes A/R profile and reports failures via
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 46b5a21..2e10464 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -26,6 +26,8 @@
'ptw.c',
))
+arm_user_ss = ss.source_set()
+
subdir('hvf')
if 'CONFIG_TCG' in config_all_accel
@@ -36,3 +38,4 @@
target_arch += {'arm': arm_ss}
target_system_arch += {'arm': arm_system_ss}
+target_user_arch += {'arm': arm_user_ss}
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
new file mode 100644
index 0000000..c059c68
--- /dev/null
+++ b/target/arm/tcg/cpu-v7m.c
@@ -0,0 +1,290 @@
+/*
+ * QEMU ARMv7-M TCG-only CPUs.
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "internals.h"
+
+#if !defined(CONFIG_USER_ONLY)
+
+#include "hw/intc/armv7m_nvic.h"
+
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ bool ret = false;
+
+ /*
+ * ARMv7-M interrupt masking works differently than -A or -R.
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
+ * masking FIQ and IRQ interrupts, an exception is taken only
+ * if it is higher priority than the current execution priority
+ * (which depends on state like BASEPRI, FAULTMASK and the
+ * currently active exception).
+ */
+ if (interrupt_request & CPU_INTERRUPT_HARD
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
+ cs->exception_index = EXCP_IRQ;
+ cc->tcg_ops->do_interrupt(cs);
+ ret = true;
+ }
+ return ret;
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+static void cortex_m0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+
+ cpu->midr = 0x410cc200;
+
+ /*
+ * These ID register values are not guest visible, because
+ * we do not implement the Main Extension. They must be set
+ * to values corresponding to the Cortex-M0's implemented
+ * features, because QEMU generally controls its emulation
+ * by looking at ID register fields. We use the same values as
+ * for the M3.
+ */
+ cpu->isar.id_pfr0 = 0x00000030;
+ cpu->isar.id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m3_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ cpu->midr = 0x410fc231;
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.id_pfr0 = 0x00000030;
+ cpu->isar.id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m4_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fc240; /* r0p0 */
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.mvfr0 = 0x10110021;
+ cpu->isar.mvfr1 = 0x11000011;
+ cpu->isar.mvfr2 = 0x00000000;
+ cpu->isar.id_pfr0 = 0x00000030;
+ cpu->isar.id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m7_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x411fc272; /* r1p2 */
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x12000011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->isar.id_pfr0 = 0x00000030;
+ cpu->isar.id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00100030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01101110;
+ cpu->isar.id_isar1 = 0x02112000;
+ cpu->isar.id_isar2 = 0x20232231;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m33_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fd213; /* r0p3 */
+ cpu->pmsav7_dregion = 16;
+ cpu->sau_sregion = 8;
+ cpu->isar.mvfr0 = 0x10110021;
+ cpu->isar.mvfr1 = 0x11000011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->isar.id_pfr0 = 0x00000030;
+ cpu->isar.id_pfr1 = 0x00000210;
+ cpu->isar.id_dfr0 = 0x00200000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00101F40;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01101110;
+ cpu->isar.id_isar1 = 0x02212000;
+ cpu->isar.id_isar2 = 0x20232232;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+ cpu->clidr = 0x00000000;
+ cpu->ctr = 0x8000c000;
+}
+
+static void cortex_m55_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fd221; /* r0p1 */
+ cpu->revidr = 0;
+ cpu->pmsav7_dregion = 16;
+ cpu->sau_sregion = 8;
+ /* These are the MVFR* values for the FPU + full MVE configuration */
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x12100211;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->isar.id_pfr0 = 0x20000030;
+ cpu->isar.id_pfr1 = 0x00000230;
+ cpu->isar.id_dfr0 = 0x10200000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00111040;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000011;
+ cpu->isar.id_isar0 = 0x01103110;
+ cpu->isar.id_isar1 = 0x02212000;
+ cpu->isar.id_isar2 = 0x20232232;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+ cpu->clidr = 0x00000000; /* caches not implemented */
+ cpu->ctr = 0x8303c003;
+}
+
+static const TCGCPUOps arm_v7m_tcg_ops = {
+ .initialize = arm_translate_init,
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
+ .debug_excp_handler = arm_debug_excp_handler,
+ .restore_state_to_opc = arm_restore_state_to_opc,
+
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = arm_cpu_record_sigsegv,
+ .record_sigbus = arm_cpu_record_sigbus,
+#else
+ .tlb_fill = arm_cpu_tlb_fill,
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
+ .debug_check_breakpoint = arm_debug_check_breakpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
+{
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ acc->info = data;
+ cc->tcg_ops = &arm_v7m_tcg_ops;
+ cc->gdb_core_xml_file = "arm-m-profile.xml";
+}
+
+static const ARMCPUInfo arm_v7m_cpus[] = {
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
+ .class_init = arm_v7m_class_init },
+};
+
+static void arm_v7m_cpu_register_types(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) {
+ arm_cpu_register(&arm_v7m_cpus[i]);
+ }
+}
+
+type_init(arm_v7m_cpu_register_types)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 6eb08a4..de8f2be 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -17,9 +17,6 @@
#include "hw/boards.h"
#endif
#include "cpregs.h"
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
-#include "hw/intc/armv7m_nvic.h"
-#endif
/* Share AArch32 -cpu max features with AArch64. */
@@ -98,32 +95,6 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-#if !defined(CONFIG_USER_ONLY)
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- CPUClass *cc = CPU_GET_CLASS(cs);
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- bool ret = false;
-
- /*
- * ARMv7-M interrupt masking works differently than -A or -R.
- * There is no FIQ/IRQ distinction. Instead of I and F bits
- * masking FIQ and IRQ interrupts, an exception is taken only
- * if it is higher priority than the current execution priority
- * (which depends on state like BASEPRI, FAULTMASK and the
- * currently active exception).
- */
- if (interrupt_request & CPU_INTERRUPT_HARD
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
- cs->exception_index = EXCP_IRQ;
- cc->tcg_ops->do_interrupt(cs);
- ret = true;
- }
- return ret;
-}
-#endif /* !CONFIG_USER_ONLY */
-
static void arm926_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -571,195 +542,6 @@
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
-static void cortex_m0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_M);
-
- cpu->midr = 0x410cc200;
-
- /*
- * These ID register values are not guest visible, because
- * we do not implement the Main Extension. They must be set
- * to values corresponding to the Cortex-M0's implemented
- * features, because QEMU generally controls its emulation
- * by looking at ID register fields. We use the same values as
- * for the M3.
- */
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m3_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- cpu->midr = 0x410fc231;
- cpu->pmsav7_dregion = 8;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m4_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x410fc240; /* r0p0 */
- cpu->pmsav7_dregion = 8;
- cpu->isar.mvfr0 = 0x10110021;
- cpu->isar.mvfr1 = 0x11000011;
- cpu->isar.mvfr2 = 0x00000000;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m7_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x411fc272; /* r1p2 */
- cpu->pmsav7_dregion = 8;
- cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x12000011;
- cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00100030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02112000;
- cpu->isar.id_isar2 = 0x20232231;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m33_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x410fd213; /* r0p3 */
- cpu->pmsav7_dregion = 16;
- cpu->sau_sregion = 8;
- cpu->isar.mvfr0 = 0x10110021;
- cpu->isar.mvfr1 = 0x11000011;
- cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000210;
- cpu->isar.id_dfr0 = 0x00200000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00101F40;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
- cpu->clidr = 0x00000000;
- cpu->ctr = 0x8000c000;
-}
-
-static void cortex_m55_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_V8_1M);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x410fd221; /* r0p1 */
- cpu->revidr = 0;
- cpu->pmsav7_dregion = 16;
- cpu->sau_sregion = 8;
- /* These are the MVFR* values for the FPU + full MVE configuration */
- cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x12100211;
- cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x20000030;
- cpu->isar.id_pfr1 = 0x00000230;
- cpu->isar.id_dfr0 = 0x10200000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00111040;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000011;
- cpu->isar.id_isar0 = 0x01103110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
- cpu->clidr = 0x00000000; /* caches not implemented */
- cpu->ctr = 0x8303c003;
-}
-
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
@@ -1127,37 +909,6 @@
cpu->reset_sctlr = 0x00000078;
}
-static const TCGCPUOps arm_v7m_tcg_ops = {
- .initialize = arm_translate_init,
- .synchronize_from_tb = arm_cpu_synchronize_from_tb,
- .debug_excp_handler = arm_debug_excp_handler,
- .restore_state_to_opc = arm_restore_state_to_opc,
-
-#ifdef CONFIG_USER_ONLY
- .record_sigsegv = arm_cpu_record_sigsegv,
- .record_sigbus = arm_cpu_record_sigbus,
-#else
- .tlb_fill = arm_cpu_tlb_fill,
- .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
- .do_interrupt = arm_v7m_cpu_do_interrupt,
- .do_transaction_failed = arm_cpu_do_transaction_failed,
- .do_unaligned_access = arm_cpu_do_unaligned_access,
- .adjust_watchpoint_address = arm_adjust_watchpoint_address,
- .debug_check_watchpoint = arm_debug_check_watchpoint,
- .debug_check_breakpoint = arm_debug_check_breakpoint,
-#endif /* !CONFIG_USER_ONLY */
-};
-
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
-{
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
-
- acc->info = data;
- cc->tcg_ops = &arm_v7m_tcg_ops;
- cc->gdb_core_xml_file = "arm-m-profile.xml";
-}
-
#ifndef TARGET_AARCH64
/*
* -cpu max: a CPU with as many features enabled as our emulation supports.
@@ -1240,18 +991,6 @@
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m55", .initfn = cortex_m55_initfn,
- .class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
{ .name = "cortex-r52", .initfn = cortex_r52_initfn },
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 5fba2c0..9f7a9f3 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1184,6 +1184,7 @@
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 6fca38f..3b1a9f0 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -55,3 +55,6 @@
arm_system_ss.add(files(
'psci.c',
))
+
+arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
+arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index 904bfda..e2e0575 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -1083,11 +1083,32 @@
}
}
-typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
+typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool);
+static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm,
+ uint8_t *pn, uint8_t *pm,
+ uint32_t desc, IMOPFn32 *fn)
+{
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
+ bool neg = simd_data(desc);
-static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
- uint8_t *pn, uint8_t *pm,
- uint32_t desc, IMOPFn *fn)
+ for (row = 0; row < oprsz; ++row) {
+ uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf;
+ uint32_t *za_row = &za[tile_vslice_index(row)];
+ uint32_t n = zn[H4(row)];
+
+ for (col = 0; col < oprsz; ++col) {
+ uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4);
+ uint32_t *a = &za_row[H4(col)];
+
+ *a = fn(n, zm[H4(col)], *a, pa & pb, neg);
+ }
+ }
+}
+
+typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool);
+static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm,
+ uint8_t *pn, uint8_t *pm,
+ uint32_t desc, IMOPFn64 *fn)
{
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
bool neg = simd_data(desc);
@@ -1107,25 +1128,16 @@
}
#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
-static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
+static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \
{ \
- uint32_t sum0 = 0, sum1 = 0; \
+ uint32_t sum = 0; \
/* Apply P to N as a mask, making the inactive elements 0. */ \
n &= expand_pred_b(p); \
- sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
- sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
- sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
- sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
- sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
- sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \
- sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
- sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \
- if (neg) { \
- sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \
- } else { \
- sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \
- } \
- return ((uint64_t)sum1 << 32) | sum0; \
+ sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
+ sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
+ sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
+ sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
+ return neg ? a - sum : a + sum; \
}
#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
@@ -1151,16 +1163,17 @@
DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
-#define DEF_IMOPH(NAME) \
- void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \
- void *vpm, uint32_t desc) \
- { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
+#define DEF_IMOPH(NAME, S) \
+ void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \
+ void *vpn, void *vpm, uint32_t desc) \
+ { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); }
-DEF_IMOPH(smopa_s)
-DEF_IMOPH(umopa_s)
-DEF_IMOPH(sumopa_s)
-DEF_IMOPH(usmopa_s)
-DEF_IMOPH(smopa_d)
-DEF_IMOPH(umopa_d)
-DEF_IMOPH(sumopa_d)
-DEF_IMOPH(usmopa_d)
+DEF_IMOPH(smopa, s)
+DEF_IMOPH(umopa, s)
+DEF_IMOPH(sumopa, s)
+DEF_IMOPH(usmopa, s)
+
+DEF_IMOPH(smopa, d)
+DEF_IMOPH(umopa, d)
+DEF_IMOPH(sumopa, d)
+DEF_IMOPH(usmopa, d)
diff --git a/target/arm/trace-events b/target/arm/trace-events
index 48cc051..4438dce 100644
--- a/target/arm/trace-events
+++ b/target/arm/trace-events
@@ -8,6 +8,7 @@
arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64
+arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64
arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
# kvm.c
diff --git a/target/i386/kvm/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c
index 778ed78..3263dcf 100644
--- a/target/i386/kvm/hyperv-stub.c
+++ b/target/i386/kvm/hyperv-stub.c
@@ -52,3 +52,7 @@
void hyperv_x86_synic_update(X86CPU *cpu)
{
}
+
+void hyperv_x86_set_vmbus_recommended_features_enabled(void)
+{
+}
diff --git a/target/i386/kvm/hyperv.c b/target/i386/kvm/hyperv.c
index 6825c89..f2a3fe6 100644
--- a/target/i386/kvm/hyperv.c
+++ b/target/i386/kvm/hyperv.c
@@ -149,3 +149,8 @@
return -1;
}
}
+
+void hyperv_x86_set_vmbus_recommended_features_enabled(void)
+{
+ hyperv_set_vmbus_recommended_features_enabled();
+}
diff --git a/target/i386/kvm/hyperv.h b/target/i386/kvm/hyperv.h
index 6754329..e3982c8 100644
--- a/target/i386/kvm/hyperv.h
+++ b/target/i386/kvm/hyperv.h
@@ -26,4 +26,6 @@
void hyperv_x86_synic_reset(X86CPU *cpu);
void hyperv_x86_synic_update(X86CPU *cpu);
+void hyperv_x86_set_vmbus_recommended_features_enabled(void);
+
#endif
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 42970ab..e68cbe9 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -1650,6 +1650,13 @@
}
}
+ /* Skip SynIC and VP_INDEX since they are hard deps already */
+ if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) &&
+ hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
+ hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
+ hyperv_x86_set_vmbus_recommended_features_enabled();
+ }
+
return 0;
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5ff0192..5a48d30 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -98,9 +98,14 @@
* instead.
*/
const RISCVIsaExtData isa_edata_arr[] = {
+ ISA_EXT_DATA_ENTRY(zic64b, PRIV_VERSION_1_12_0, ext_zic64b),
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
+ ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, ext_always_enabled),
+ ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, ext_always_enabled),
+ ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, ext_always_enabled),
+ ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_always_enabled),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
@@ -109,6 +114,7 @@
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
+ ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, ext_always_enabled),
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
@@ -143,6 +149,7 @@
ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
+ ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso),
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
@@ -172,8 +179,13 @@
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
+ ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, ext_always_enabled),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
+ ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, ext_always_enabled),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
+ ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, ext_always_enabled),
+ ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, ext_always_enabled),
+ ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
@@ -949,9 +961,9 @@
env->two_stage_lookup = false;
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
- (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
- env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
- (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
+ (!cpu->cfg.ext_svade && cpu->cfg.ext_svadu ?
+ MENVCFG_ADUE : 0);
+ env->henvcfg = 0;
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
@@ -1452,17 +1464,27 @@
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
+ MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
+ MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
+ MULTI_EXT_CFG_BOOL("zfbfmin", ext_zfbfmin, false),
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
+ MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
+ MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
+ MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
+ MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
+ MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
+ MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
+ MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
@@ -1488,6 +1510,7 @@
MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
+ MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false),
MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
@@ -1549,25 +1572,40 @@
/* These are experimental so mark with 'x-' */
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
- MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
- MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
-
- MULTI_EXT_CFG_BOOL("x-zaamo", ext_zaamo, false),
- MULTI_EXT_CFG_BOOL("x-zalrsc", ext_zalrsc, false),
-
- MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
- MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
-
- MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
- MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
- MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
-
DEFINE_PROP_END_OF_LIST(),
};
+#define ALWAYS_ENABLED_FEATURE(_name) \
+ {.name = _name, \
+ .offset = CPU_CFG_OFFSET(ext_always_enabled), \
+ .enabled = true}
+
+/*
+ * 'Named features' is the name we give to extensions that we
+ * don't want to expose to users. They are either immutable
+ * (always enabled/disable) or they'll vary depending on
+ * the resulting CPU state. They have riscv,isa strings
+ * and priv_ver like regular extensions.
+ */
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
- MULTI_EXT_CFG_BOOL("svade", svade, true),
- MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
+ MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
+
+ /*
+ * cache-related extensions that are always enabled
+ * in TCG since QEMU RISC-V does not have a cache
+ * model.
+ */
+ ALWAYS_ENABLED_FEATURE("za64rs"),
+ ALWAYS_ENABLED_FEATURE("ziccif"),
+ ALWAYS_ENABLED_FEATURE("ziccrse"),
+ ALWAYS_ENABLED_FEATURE("ziccamoa"),
+ ALWAYS_ENABLED_FEATURE("zicclsm"),
+ ALWAYS_ENABLED_FEATURE("ssccptr"),
+
+ /* Other named features that TCG always implements */
+ ALWAYS_ENABLED_FEATURE("sstvecd"),
+ ALWAYS_ENABLED_FEATURE("sstvala"),
+ ALWAYS_ENABLED_FEATURE("sscounterenw"),
DEFINE_PROP_END_OF_LIST(),
};
@@ -2162,13 +2200,10 @@
};
/*
- * RVA22U64 defines some 'named features' or 'synthetic extensions'
- * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
- * and Zicclsm. We do not implement caching in QEMU so we'll consider
- * all these named features as always enabled.
- *
- * There's no riscv,isa update for them (nor for zic64b, despite it
- * having a cfg offset) at this moment.
+ * RVA22U64 defines some 'named features' that are cache
+ * related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
+ * and Zicclsm. They are always implemented in TCG and
+ * doesn't need to be manually enabled by the profile.
*/
static RISCVCPUProfile RVA22U64 = {
.parent = NULL,
@@ -2185,7 +2220,7 @@
CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
/* mandatory named features for this profile */
- CPU_CFG_OFFSET(zic64b),
+ CPU_CFG_OFFSET(ext_zic64b),
RISCV_PROFILE_EXT_LIST_END
}
@@ -2200,8 +2235,6 @@
* Other named features that we already implement: Sstvecd, Sstvala,
* Sscounterenw
*
- * Named features that we need to enable: svade
- *
* The remaining features/extensions comes from RVA22U64.
*/
static RISCVCPUProfile RVA22S64 = {
@@ -2213,10 +2246,7 @@
.ext_offsets = {
/* rva22s64 exts */
CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
- CPU_CFG_OFFSET(ext_svinval),
-
- /* rva22s64 named features */
- CPU_CFG_OFFSET(svade),
+ CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
RISCV_PROFILE_EXT_LIST_END
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5d291a7..3b1a02b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -271,7 +271,7 @@
target_ulong hstatus;
target_ulong hedeleg;
uint64_t hideleg;
- target_ulong hcounteren;
+ uint32_t hcounteren;
target_ulong htval;
target_ulong htinst;
target_ulong hgatp;
@@ -334,10 +334,10 @@
*/
bool two_stage_indirect_lookup;
- target_ulong scounteren;
- target_ulong mcounteren;
+ uint32_t scounteren;
+ uint32_t mcounteren;
- target_ulong mcountinhibit;
+ uint32_t mcountinhibit;
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 833bf58..2040b90 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -71,6 +71,7 @@
bool ext_zihintntl;
bool ext_zihintpause;
bool ext_zihpm;
+ bool ext_ztso;
bool ext_smstateen;
bool ext_sstc;
bool ext_svadu;
@@ -119,13 +120,21 @@
bool ext_smepmp;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
- bool svade;
- bool zic64b;
uint32_t mvendorid;
uint64_t marchid;
uint64_t mimpid;
+ /* Named features */
+ bool ext_svade;
+ bool ext_zic64b;
+
+ /*
+ * Always 'true' boolean for named features
+ * TCG always implement/can't be disabled.
+ */
+ bool ext_always_enabled;
+
/* Vendor-specific custom extensions */
bool ext_xtheadba;
bool ext_xtheadbb;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d462d95..ce73220 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -907,7 +907,9 @@
}
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
- bool adue = env->menvcfg & MENVCFG_ADUE;
+ bool svade = riscv_cpu_cfg(env)->ext_svade;
+ bool svadu = riscv_cpu_cfg(env)->ext_svadu;
+ bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
if (first_stage && two_stage && env->virt_enabled) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
@@ -1082,9 +1084,18 @@
return TRANSLATE_FAIL;
}
- /* If necessary, set accessed and dirty bits. */
- target_ulong updated_pte = pte | PTE_A |
- (access_type == MMU_DATA_STORE ? PTE_D : 0);
+ target_ulong updated_pte = pte;
+
+ /*
+ * If ADUE is enabled, set accessed and dirty bits.
+ * Otherwise raise an exception if necessary.
+ */
+ if (adue) {
+ updated_pte |= PTE_A | (access_type == MMU_DATA_STORE ? PTE_D : 0);
+ } else if (!(pte & PTE_A) ||
+ (access_type == MMU_DATA_STORE && !(pte & PTE_D))) {
+ return TRANSLATE_FAIL;
+ }
/* Page table updates need to be atomic with MTTCG enabled */
if (updated_pte != pte && !is_debug) {
@@ -1212,7 +1223,7 @@
if (env->virt_enabled) {
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
- 0, mmu_idx, false, true, true)) {
+ 0, MMUIdx_U, false, true, true)) {
return -1;
}
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d4e8ac1..7260964 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1295,8 +1295,34 @@
static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
- return (vm & 0xf) <=
- satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
+ uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
+ return get_field(mode_supported, (1 << vm));
+}
+
+static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp,
+ target_ulong val)
+{
+ target_ulong mask;
+ bool vm;
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
+ mask = (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
+ } else {
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
+ mask = (val ^ old_xatp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
+ }
+
+ if (vm && mask) {
+ /*
+ * The ISA defines SATP.MODE=Bare as "no translation", but we still
+ * pass these through QEMU's TLB emulation as it improves
+ * performance. Flushing the TLB on SATP writes with paging
+ * enabled avoids leaking those invalid cached mappings.
+ */
+ tlb_flush(env_cpu(env));
+ return val;
+ }
+ return old_xatp;
}
static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
@@ -2133,7 +2159,7 @@
/*
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
- * henvcfg.hade is read_only 0 when menvcfg.hade = 0
+ * henvcfg.adue is read_only 0 when menvcfg.adue = 0
*/
*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
env->menvcfg);
@@ -3021,31 +3047,11 @@
static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val)
{
- target_ulong mask;
- bool vm;
-
if (!riscv_cpu_cfg(env)->mmu) {
return RISCV_EXCP_NONE;
}
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- vm = validate_vm(env, get_field(val, SATP32_MODE));
- mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
- } else {
- vm = validate_vm(env, get_field(val, SATP64_MODE));
- mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
- }
-
- if (vm && mask) {
- /*
- * The ISA defines SATP.MODE=Bare as "no translation", but we still
- * pass these through QEMU's TLB emulation as it improves
- * performance. Flushing the TLB on SATP writes with paging
- * enabled avoids leaking those invalid cached mappings.
- */
- tlb_flush(env_cpu(env));
- env->satp = val;
- }
+ env->satp = legalize_xatp(env, env->satp, val);
return RISCV_EXCP_NONE;
}
@@ -3532,7 +3538,7 @@
static RISCVException write_hgatp(CPURISCVState *env, int csrno,
target_ulong val)
{
- env->hgatp = val;
+ env->hgatp = legalize_xatp(env, env->hgatp, val);
return RISCV_EXCP_NONE;
}
@@ -3809,7 +3815,7 @@
static RISCVException write_vsatp(CPURISCVState *env, int csrno,
target_ulong val)
{
- env->vsatp = val;
+ env->vsatp = legalize_xatp(env, env->vsatp, val);
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 267930e..4a9e459 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -40,7 +40,11 @@
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
- if (a->aq) {
+ /*
+ * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
+ * AMOs. Instead treat them like loads.
+ */
+ if (a->aq || ctx->ztso) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
@@ -76,9 +80,10 @@
gen_set_label(l1);
/*
* Address comparison failure. However, we still need to
- * provide the memory barrier implied by AQ/RL.
+ * provide the memory barrier implied by AQ/RL/TSO.
*/
- tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+ TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
gen_set_label(l2);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index faf6d65..ad40d3e 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -266,12 +266,20 @@
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
+ bool out;
+
decode_save_opc(ctx);
if (get_xl(ctx) == MXL_RV128) {
- return gen_load_i128(ctx, a, memop);
+ out = gen_load_i128(ctx, a, memop);
} else {
- return gen_load_tl(ctx, a, memop);
+ out = gen_load_tl(ctx, a, memop);
}
+
+ if (ctx->ztso) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+
+ return out;
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
@@ -328,6 +336,10 @@
TCGv addr = get_address(ctx, a->rs1, a->imm);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
+ if (ctx->ztso) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9e101ab..e427289 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -636,10 +636,28 @@
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
+ /*
+ * According to the specification
+ *
+ * Additionally, if the Ztso extension is implemented, then vector memory
+ * instructions in the V extension and Zve family of extensions follow
+ * RVTSO at the instruction level. The Ztso extension does not
+ * strengthen the ordering of intra-instruction element accesses.
+ *
+ * as a result neither ordered nor unordered accesses from the V
+ * instructions need ordering within the loop but we do still need barriers
+ * around the loop.
+ */
+ if (is_store && s->ztso) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+
+ mark_vs_dirty(s);
+
fn(dest, mask, base, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
+ if (!is_store && s->ztso) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
gen_set_label(over);
@@ -778,7 +796,7 @@
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
uint32_t data, gen_helper_ldst_stride *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
TCGv_ptr dest, mask;
TCGv base, stride;
@@ -797,11 +815,9 @@
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, stride, tcg_env, desc);
+ mark_vs_dirty(s);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ fn(dest, mask, base, stride, tcg_env, desc);
gen_set_label(over);
return true;
@@ -827,7 +843,7 @@
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -861,7 +877,7 @@
return false;
}
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -884,7 +900,7 @@
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
uint32_t data, gen_helper_ldst_index *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
TCGv_ptr dest, mask, index;
TCGv base;
@@ -904,11 +920,9 @@
tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, index, tcg_env, desc);
+ mark_vs_dirty(s);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ fn(dest, mask, base, index, tcg_env, desc);
gen_set_label(over);
return true;
@@ -953,7 +967,7 @@
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -1005,7 +1019,7 @@
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -1084,7 +1098,7 @@
static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t width, gen_helper_ldst_whole *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
uint32_t evl = s->cfg_ptr->vlenb * nf / width;
TCGLabel *over = gen_new_label();
@@ -1102,11 +1116,10 @@
base = get_gpr(s, rs1, EXT_NONE);
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ mark_vs_dirty(s);
+
fn(dest, base, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
- }
gen_set_label(over);
return true;
@@ -1116,42 +1129,42 @@
* load and store whole register instructions ignore vtype and vl setting.
* Thus, we don't need to check vill bit. (Section 7.9)
*/
-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
{ \
if (require_rvv(s) && \
QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \
- gen_helper_##NAME, s, IS_STORE); \
+ gen_helper_##NAME, s); \
} \
return false; \
}
-GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false)
-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
-GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false)
-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
-GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false)
-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
-GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false)
-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
+GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1)
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2)
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4)
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8)
+GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1)
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2)
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4)
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8)
+GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1)
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2)
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4)
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8)
+GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1)
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2)
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4)
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8)
/*
* The vector whole register store instructions are encoded similar to
* unmasked unit-stride store of elements with EEW=8.
*/
-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1)
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1)
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1)
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1)
/*
*** Vector Integer Arithmetic Instructions
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index 2d992e1..cd234ad 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -293,12 +293,14 @@
{
REQUIRE_ZCMT(ctx);
+ TCGv addr = tcg_temp_new();
+
/*
* Update pc to current for the non-unwinding exception
* that might come from cpu_ld*_code() in the helper.
*/
gen_update_pc(ctx, 0);
- gen_helper_cm_jalt(cpu_pc, tcg_env, tcg_constant_i32(a->index));
+ gen_helper_cm_jalt(addr, tcg_env, tcg_constant_i32(a->index));
/* c.jt vs c.jalt depends on the index. */
if (a->index >= 32) {
@@ -307,6 +309,8 @@
gen_set_gpr(ctx, xRA, succ_pc);
}
+ tcg_gen_mov_tl(cpu_pc, addr);
+
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
return true;
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 422e4f1..c7afdb1 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -275,13 +275,42 @@
KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR),
+ KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND),
KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR),
KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI),
+ KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL),
KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM),
+ KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA),
+ KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH),
+ KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN),
KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA),
KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
+ KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC),
+ KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB),
+ KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC),
+ KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX),
KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS),
+ KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND),
+ KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE),
+ KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH),
+ KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR),
+ KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED),
+ KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH),
+ KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT),
+ KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB),
+ KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC),
+ KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH),
+ KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN),
+ KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB),
+ KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG),
+ KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED),
+ KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA),
+ KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB),
+ KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED),
+ KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH),
+ KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT),
+ KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN),
KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC),
KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 81cf228..76f2150 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -79,14 +79,14 @@
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
- .version_id = 3,
- .minimum_version_id = 3,
+ .version_id = 4,
+ .minimum_version_id = 4,
.needed = hyper_needed,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL(env.hstatus, RISCVCPU),
VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
VMSTATE_UINT64(env.hideleg, RISCVCPU),
- VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
+ VMSTATE_UINT32(env.hcounteren, RISCVCPU),
VMSTATE_UINTTL(env.htval, RISCVCPU),
VMSTATE_UINTTL(env.htinst, RISCVCPU),
VMSTATE_UINTTL(env.hgatp, RISCVCPU),
@@ -353,8 +353,8 @@
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 9,
- .minimum_version_id = 9,
+ .version_id = 10,
+ .minimum_version_id = 10,
.post_load = riscv_cpu_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -397,9 +397,9 @@
VMSTATE_UINTTL(env.mtval, RISCVCPU),
VMSTATE_UINTTL(env.miselect, RISCVCPU),
VMSTATE_UINTTL(env.siselect, RISCVCPU),
- VMSTATE_UINTTL(env.scounteren, RISCVCPU),
- VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
- VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
+ VMSTATE_UINT32(env.scounteren, RISCVCPU),
+ VMSTATE_UINT32(env.mcounteren, RISCVCPU),
+ VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
vmstate_pmu_ctr_state, PMUCTRState),
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 505fc85..7c0ad66 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -16,6 +16,9 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#ifndef RISCV_PMU_H
+#define RISCV_PMU_H
+
#include "cpu.h"
#include "qapi/error.h"
@@ -31,3 +34,5 @@
void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
+
+#endif /* RISCV_PMU_H */
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index dd5228c..ab6db81 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -196,17 +196,14 @@
static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
{
- switch (feat_offset) {
- case CPU_CFG_OFFSET(zic64b):
+ /*
+ * All other named features are already enabled
+ * in riscv_tcg_cpu_instance_init().
+ */
+ if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) {
cpu->cfg.cbom_blocksize = 64;
cpu->cfg.cbop_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
- break;
- case CPU_CFG_OFFSET(svade):
- cpu->cfg.ext_svadu = false;
- break;
- default:
- g_assert_not_reached();
}
}
@@ -219,10 +216,6 @@
return;
}
- if (cpu_cfg_offset_is_named_feat(ext_offset)) {
- return;
- }
-
ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset);
if (env->priv_ver < ext_priv_ver) {
@@ -322,11 +315,9 @@
static void riscv_cpu_update_named_features(RISCVCPU *cpu)
{
- cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 &&
- cpu->cfg.cbop_blocksize == 64 &&
- cpu->cfg.cboz_blocksize == 64;
-
- cpu->cfg.svade = !cpu->cfg.ext_svadu;
+ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
+ cpu->cfg.cbop_blocksize == 64 &&
+ cpu->cfg.cboz_blocksize == 64;
}
static void riscv_cpu_validate_g(RISCVCPU *cpu)
@@ -1075,6 +1066,7 @@
#ifndef CONFIG_USER_ONLY
if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
+ object_property_set_bool(obj, "mmu", true, NULL);
const char *satp_prop = satp_mode_str(profile->satp_mode,
riscv_cpu_is_32bit(cpu));
object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
@@ -1290,6 +1282,12 @@
isa_ext_update_enabled(cpu, prop->offset, true);
}
+ /*
+ * Some extensions can't be added without backward compatibilty concerns.
+ * Disable those, the user can still opt in to them on the command line.
+ */
+ cpu->cfg.ext_svade = false;
+
/* set vector version */
env->vext_ver = VEXT_VERSION_1_00_0;
@@ -1318,6 +1316,8 @@
RISCVCPU *cpu = RISCV_CPU(cs);
Object *obj = OBJECT(cpu);
+ cpu->cfg.ext_always_enabled = true;
+
misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
riscv_cpu_add_user_properties(obj);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 177418b..ea5d52b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -109,6 +109,8 @@
/* PointerMasking extension */
bool pm_mask_enabled;
bool pm_base_enabled;
+ /* Ztso */
+ bool ztso;
/* Use icount trigger for native debug */
bool itrigger;
/* FRM is known to contain a valid value. */
@@ -1196,6 +1198,7 @@
ctx->cs = cs;
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
+ ctx->ztso = cpu->cfg.ext_ztso;
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73..fe56c00 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -44,6 +44,7 @@
target_ulong reserved = s2 &
MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
+ uint16_t vlen = cpu->cfg.vlenb << 3;
int8_t lmul;
if (vlmul & 4) {
@@ -53,10 +54,8 @@
* VLEN * LMUL >= SEW
* VLEN >> (8 - lmul) >= sew
* (vlenb << 3) >> (8 - lmul) >= sew
- * vlenb >> (8 - 3 - lmul) >= sew
*/
- if (vlmul == 4 ||
- cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
+ if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
vill = true;
}
}
diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build
index 90aae42..3aed6ef 100644
--- a/tests/qtest/libqos/meson.build
+++ b/tests/qtest/libqos/meson.build
@@ -60,6 +60,7 @@
'arm-xilinx-zynq-a9-machine.c',
'ppc64_pseries-machine.c',
'x86_64_pc-machine.c',
+ 'riscv-virt-machine.c',
)
if have_virtfs
diff --git a/tests/qtest/libqos/riscv-virt-machine.c b/tests/qtest/libqos/riscv-virt-machine.c
new file mode 100644
index 0000000..c4364c9
--- /dev/null
+++ b/tests/qtest/libqos/riscv-virt-machine.c
@@ -0,0 +1,137 @@
+/*
+ * libqos driver framework for risc-v
+ *
+ * Initial version based on arm-virt-machine.c
+ *
+ * Copyright (c) 2024 Ventana Micro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2.1 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include "qemu/osdep.h"
+#include "../libqtest.h"
+#include "qemu/module.h"
+#include "libqos-malloc.h"
+#include "qgraph.h"
+#include "virtio-mmio.h"
+#include "generic-pcihost.h"
+#include "hw/pci/pci_regs.h"
+
+#define RISCV_PAGE_SIZE 4096
+
+/* VIRT_DRAM */
+#define RISCV_VIRT_RAM_ADDR 0x80000000
+#define RISCV_VIRT_RAM_SIZE 0x20000000
+
+/*
+ * VIRT_VIRTIO. BASE_ADDR points to the last
+ * virtio_mmio device.
+ */
+#define VIRTIO_MMIO_BASE_ADDR 0x10008000
+#define VIRTIO_MMIO_SIZE 0x00001000
+
+/* VIRT_PCIE_PIO */
+#define RISCV_GPEX_PIO_BASE 0x3000000
+#define RISCV_BUS_PIO_LIMIT 0x10000
+
+/* VIRT_PCIE_MMIO */
+#define RISCV_BUS_MMIO_ALLOC_PTR 0x40000000
+#define RISCV_BUS_MMIO_LIMIT 0x80000000
+
+/* VIRT_PCIE_ECAM */
+#define RISCV_ECAM_ALLOC_PTR 0x30000000
+
+typedef struct QVirtMachine QVirtMachine;
+
+struct QVirtMachine {
+ QOSGraphObject obj;
+ QGuestAllocator alloc;
+ QVirtioMMIODevice virtio_mmio;
+ QGenericPCIHost bridge;
+};
+
+static void virt_destructor(QOSGraphObject *obj)
+{
+ QVirtMachine *machine = (QVirtMachine *) obj;
+ alloc_destroy(&machine->alloc);
+}
+
+static void *virt_get_driver(void *object, const char *interface)
+{
+ QVirtMachine *machine = object;
+ if (!g_strcmp0(interface, "memory")) {
+ return &machine->alloc;
+ }
+
+ fprintf(stderr, "%s not present in riscv/virtio\n", interface);
+ g_assert_not_reached();
+}
+
+static QOSGraphObject *virt_get_device(void *obj, const char *device)
+{
+ QVirtMachine *machine = obj;
+ if (!g_strcmp0(device, "generic-pcihost")) {
+ return &machine->bridge.obj;
+ } else if (!g_strcmp0(device, "virtio-mmio")) {
+ return &machine->virtio_mmio.obj;
+ }
+
+ fprintf(stderr, "%s not present in riscv/virt\n", device);
+ g_assert_not_reached();
+}
+
+static void riscv_config_qpci_bus(QGenericPCIBus *qpci)
+{
+ qpci->gpex_pio_base = RISCV_GPEX_PIO_BASE;
+ qpci->bus.pio_limit = RISCV_BUS_PIO_LIMIT;
+
+ qpci->bus.mmio_alloc_ptr = RISCV_BUS_MMIO_ALLOC_PTR;
+ qpci->bus.mmio_limit = RISCV_BUS_MMIO_LIMIT;
+
+ qpci->ecam_alloc_ptr = RISCV_ECAM_ALLOC_PTR;
+}
+
+static void *qos_create_machine_riscv_virt(QTestState *qts)
+{
+ QVirtMachine *machine = g_new0(QVirtMachine, 1);
+
+ alloc_init(&machine->alloc, 0,
+ RISCV_VIRT_RAM_ADDR,
+ RISCV_VIRT_RAM_ADDR + RISCV_VIRT_RAM_SIZE,
+ RISCV_PAGE_SIZE);
+ qvirtio_mmio_init_device(&machine->virtio_mmio, qts, VIRTIO_MMIO_BASE_ADDR,
+ VIRTIO_MMIO_SIZE);
+
+ qos_create_generic_pcihost(&machine->bridge, qts, &machine->alloc);
+ riscv_config_qpci_bus(&machine->bridge.pci);
+
+ machine->obj.get_device = virt_get_device;
+ machine->obj.get_driver = virt_get_driver;
+ machine->obj.destructor = virt_destructor;
+ return machine;
+}
+
+static void virt_machine_register_nodes(void)
+{
+ qos_node_create_machine_args("riscv32/virt", qos_create_machine_riscv_virt,
+ "aclint=on,aia=aplic-imsic");
+ qos_node_contains("riscv32/virt", "virtio-mmio", NULL);
+ qos_node_contains("riscv32/virt", "generic-pcihost", NULL);
+
+ qos_node_create_machine_args("riscv64/virt", qos_create_machine_riscv_virt,
+ "aclint=on,aia=aplic-imsic");
+ qos_node_contains("riscv64/virt", "virtio-mmio", NULL);
+ qos_node_contains("riscv64/virt", "generic-pcihost", NULL);
+}
+
+libqos_init(virt_machine_register_nodes);
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 31b9f4e..36c5c13 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -204,7 +204,8 @@
qtests_stm32l4x5 = \
['stm32l4x5_exti-test',
'stm32l4x5_syscfg-test',
- 'stm32l4x5_rcc-test']
+ 'stm32l4x5_rcc-test',
+ 'stm32l4x5_gpio-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
new file mode 100644
index 0000000..cc56be2
--- /dev/null
+++ b/tests/qtest/stm32l4x5_gpio-test.c
@@ -0,0 +1,551 @@
+/*
+ * QTest testcase for STM32L4x5_GPIO
+ *
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+#define GPIO_BASE_ADDR 0x48000000
+#define GPIO_SIZE 0x400
+#define NUM_GPIOS 8
+#define NUM_GPIO_PINS 16
+
+#define GPIO_A 0x48000000
+#define GPIO_B 0x48000400
+#define GPIO_C 0x48000800
+#define GPIO_D 0x48000C00
+#define GPIO_E 0x48001000
+#define GPIO_F 0x48001400
+#define GPIO_G 0x48001800
+#define GPIO_H 0x48001C00
+
+#define MODER 0x00
+#define OTYPER 0x04
+#define PUPDR 0x0C
+#define IDR 0x10
+#define ODR 0x14
+#define BSRR 0x18
+#define BRR 0x28
+
+#define MODER_INPUT 0
+#define MODER_OUTPUT 1
+
+#define PUPDR_NONE 0
+#define PUPDR_PULLUP 1
+#define PUPDR_PULLDOWN 2
+
+#define OTYPER_PUSH_PULL 0
+#define OTYPER_OPEN_DRAIN 1
+
+const uint32_t moder_reset[NUM_GPIOS] = {
+ 0xABFFFFFF,
+ 0xFFFFFEBF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0x0000000F
+};
+
+const uint32_t pupdr_reset[NUM_GPIOS] = {
+ 0x64000000,
+ 0x00000100,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+const uint32_t idr_reset[NUM_GPIOS] = {
+ 0x0000A000,
+ 0x00000010,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
+{
+ return readl(gpio + offset);
+}
+
+static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value)
+{
+ writel(gpio + offset, value);
+}
+
+static void gpio_set_bit(unsigned int gpio, unsigned int reg,
+ unsigned int pin, uint32_t value)
+{
+ uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin);
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin);
+}
+
+static void gpio_set_2bits(unsigned int gpio, unsigned int reg,
+ unsigned int pin, uint32_t value)
+{
+ uint32_t offset = 2 * pin;
+ uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset);
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset);
+}
+
+static unsigned int get_gpio_id(uint32_t gpio_addr)
+{
+ return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE;
+}
+
+static void gpio_set_irq(unsigned int gpio, int num, int level)
+{
+ g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c",
+ get_gpio_id(gpio) + 'a');
+ qtest_set_irq_in(global_qtest, name, NULL, num, level);
+}
+
+static void disconnect_all_pins(unsigned int gpio)
+{
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
+ get_gpio_id(gpio) + 'a');
+ QDict *r;
+
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': "
+ "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }",
+ path, 0xFFFF);
+ g_assert_false(qdict_haskey(r, "error"));
+ qobject_unref(r);
+}
+
+static uint32_t get_disconnected_pins(unsigned int gpio)
+{
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
+ get_gpio_id(gpio) + 'a');
+ uint32_t disconnected_pins = 0;
+ QDict *r;
+
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':"
+ " { 'path': %s, 'property': 'disconnected-pins'} }", path);
+ g_assert_false(qdict_haskey(r, "error"));
+ disconnected_pins = qdict_get_int(r, "return");
+ qobject_unref(r);
+ return disconnected_pins;
+}
+
+static uint32_t reset(uint32_t gpio, unsigned int offset)
+{
+ switch (offset) {
+ case MODER:
+ return moder_reset[get_gpio_id(gpio)];
+ case PUPDR:
+ return pupdr_reset[get_gpio_id(gpio)];
+ case IDR:
+ return idr_reset[get_gpio_id(gpio)];
+ }
+ return 0x0;
+}
+
+static void system_reset(void)
+{
+ QDict *r;
+ r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
+ g_assert_false(qdict_haskey(r, "error"));
+ qobject_unref(r);
+}
+
+static void test_idr_reset_value(void)
+{
+ /*
+ * Checks that the values in MODER, OTYPER, PUPDR and ODR
+ * after reset are correct, and that the value in IDR is
+ * coherent.
+ * Since AF and analog modes aren't implemented, IDR reset
+ * values aren't the same as with a real board.
+ *
+ * Register IDR contains the actual values of all GPIO pins.
+ * Its value depends on the pins' configuration
+ * (intput/output/analog : register MODER, push-pull/open-drain :
+ * register OTYPER, pull-up/pull-down/none : register PUPDR)
+ * and on the values stored in register ODR
+ * (in case the pin is in output mode).
+ */
+
+ gpio_writel(GPIO_A, MODER, 0xDEADBEEF);
+ gpio_writel(GPIO_A, ODR, 0xDEADBEEF);
+ gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF);
+ gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF);
+
+ gpio_writel(GPIO_B, MODER, 0xDEADBEEF);
+ gpio_writel(GPIO_B, ODR, 0xDEADBEEF);
+ gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF);
+ gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF);
+
+ gpio_writel(GPIO_C, MODER, 0xDEADBEEF);
+ gpio_writel(GPIO_C, ODR, 0xDEADBEEF);
+ gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF);
+ gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF);
+
+ gpio_writel(GPIO_H, MODER, 0xDEADBEEF);
+ gpio_writel(GPIO_H, ODR, 0xDEADBEEF);
+ gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF);
+ gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF);
+
+ system_reset();
+
+ uint32_t moder = gpio_readl(GPIO_A, MODER);
+ uint32_t odr = gpio_readl(GPIO_A, ODR);
+ uint32_t otyper = gpio_readl(GPIO_A, OTYPER);
+ uint32_t pupdr = gpio_readl(GPIO_A, PUPDR);
+ uint32_t idr = gpio_readl(GPIO_A, IDR);
+ /* 15: AF, 14: AF, 13: AF, 12: Analog ... */
+ /* here AF is the same as Analog and Input mode */
+ g_assert_cmphex(moder, ==, reset(GPIO_A, MODER));
+ g_assert_cmphex(odr, ==, reset(GPIO_A, ODR));
+ g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER));
+ /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */
+ g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR));
+ /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */
+ g_assert_cmphex(idr, ==, reset(GPIO_A, IDR));
+
+ moder = gpio_readl(GPIO_B, MODER);
+ odr = gpio_readl(GPIO_B, ODR);
+ otyper = gpio_readl(GPIO_B, OTYPER);
+ pupdr = gpio_readl(GPIO_B, PUPDR);
+ idr = gpio_readl(GPIO_B, IDR);
+ /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */
+ /* here AF is the same as Analog and Input mode */
+ g_assert_cmphex(moder, ==, reset(GPIO_B, MODER));
+ g_assert_cmphex(odr, ==, reset(GPIO_B, ODR));
+ g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER));
+ /* ... 5: neither, 4: pull-up, 3: neither ... */
+ g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR));
+ /* ... 5 : reset value, 4 : 1, 3 : reset value ... */
+ g_assert_cmphex(idr, ==, reset(GPIO_B, IDR));
+
+ moder = gpio_readl(GPIO_C, MODER);
+ odr = gpio_readl(GPIO_C, ODR);
+ otyper = gpio_readl(GPIO_C, OTYPER);
+ pupdr = gpio_readl(GPIO_C, PUPDR);
+ idr = gpio_readl(GPIO_C, IDR);
+ /* Analog, same as Input mode*/
+ g_assert_cmphex(moder, ==, reset(GPIO_C, MODER));
+ g_assert_cmphex(odr, ==, reset(GPIO_C, ODR));
+ g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER));
+ /* no pull-up or pull-down */
+ g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR));
+ /* reset value */
+ g_assert_cmphex(idr, ==, reset(GPIO_C, IDR));
+
+ moder = gpio_readl(GPIO_H, MODER);
+ odr = gpio_readl(GPIO_H, ODR);
+ otyper = gpio_readl(GPIO_H, OTYPER);
+ pupdr = gpio_readl(GPIO_H, PUPDR);
+ idr = gpio_readl(GPIO_H, IDR);
+ /* Analog, same as Input mode */
+ g_assert_cmphex(moder, ==, reset(GPIO_H, MODER));
+ g_assert_cmphex(odr, ==, reset(GPIO_H, ODR));
+ g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER));
+ /* no pull-up or pull-down */
+ g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR));
+ /* reset value */
+ g_assert_cmphex(idr, ==, reset(GPIO_H, IDR));
+}
+
+static void test_gpio_output_mode(const void *data)
+{
+ /*
+ * Checks that setting a bit in ODR sets the corresponding
+ * GPIO line high : it should set the right bit in IDR
+ * and send an irq to syscfg.
+ * Additionally, it checks that values written to ODR
+ * when not in output mode are stored and not discarded.
+ */
+ unsigned int pin = ((uint64_t)data) & 0xF;
+ uint32_t gpio = ((uint64_t)data) >> 32;
+ unsigned int gpio_id = get_gpio_id(gpio);
+
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+
+ /* Set a bit in ODR and check nothing happens */
+ gpio_set_bit(gpio, ODR, pin, 1);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+
+ /* Configure the relevant line as output and check the pin is high */
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+
+ /* Reset the bit in ODR and check the pin is low */
+ gpio_set_bit(gpio, ODR, pin, 0);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+
+ /* Clean the test */
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+}
+
+static void test_gpio_input_mode(const void *data)
+{
+ /*
+ * Test that setting a line high/low externally sets the
+ * corresponding GPIO line high/low : it should set the
+ * right bit in IDR and send an irq to syscfg.
+ */
+ unsigned int pin = ((uint64_t)data) & 0xF;
+ uint32_t gpio = ((uint64_t)data) >> 32;
+ unsigned int gpio_id = get_gpio_id(gpio);
+
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+
+ /* Configure a line as input, raise it, and check that the pin is high */
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
+ gpio_set_irq(gpio, pin, 1);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+
+ /* Lower the line and check that the pin is low */
+ gpio_set_irq(gpio, pin, 0);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+
+ /* Clean the test */
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
+ disconnect_all_pins(gpio);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
+}
+
+static void test_pull_up_pull_down(const void *data)
+{
+ /*
+ * Test that a floating pin with pull-up sets the pin
+ * high and vice-versa.
+ */
+ unsigned int pin = ((uint64_t)data) & 0xF;
+ uint32_t gpio = ((uint64_t)data) >> 32;
+ unsigned int gpio_id = get_gpio_id(gpio);
+
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+
+ /* Configure a line as input with pull-up, check the line is set high */
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+
+ /* Configure the line with pull-down, check the line is low */
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
+
+ /* Clean the test */
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
+ gpio_writel(gpio, PUPDR, reset(gpio, PUPDR));
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
+}
+
+static void test_push_pull(const void *data)
+{
+ /*
+ * Test that configuring a line in push-pull output mode
+ * disconnects the pin, that the pin can't be set or reset
+ * externally afterwards.
+ */
+ unsigned int pin = ((uint64_t)data) & 0xF;
+ uint32_t gpio = ((uint64_t)data) >> 32;
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
+
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+
+ /* Setting a line high externally, configuring it in push-pull output */
+ /* And checking the pin was disconnected */
+ gpio_set_irq(gpio, pin, 1);
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
+
+ /* Setting a line low externally, configuring it in push-pull output */
+ /* And checking the pin was disconnected */
+ gpio_set_irq(gpio2, pin, 0);
+ gpio_set_bit(gpio2, ODR, pin, 1);
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
+
+ /* Trying to set a push-pull output pin, checking it doesn't work */
+ gpio_set_irq(gpio, pin, 1);
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
+
+ /* Trying to reset a push-pull output pin, checking it doesn't work */
+ gpio_set_irq(gpio2, pin, 0);
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
+
+ /* Clean the test */
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
+}
+
+static void test_open_drain(const void *data)
+{
+ /*
+ * Test that configuring a line in open-drain output mode
+ * disconnects a pin set high externally and that the pin
+ * can't be set high externally while configured in open-drain.
+ *
+ * However a pin set low externally shouldn't be disconnected,
+ * and it can be set low externally when in open-drain mode.
+ */
+ unsigned int pin = ((uint64_t)data) & 0xF;
+ uint32_t gpio = ((uint64_t)data) >> 32;
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
+
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+
+ /* Setting a line high externally, configuring it in open-drain output */
+ /* And checking the pin was disconnected */
+ gpio_set_irq(gpio, pin, 1);
+ gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN);
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
+
+ /* Setting a line low externally, configuring it in open-drain output */
+ /* And checking the pin wasn't disconnected */
+ gpio_set_irq(gpio2, pin, 0);
+ gpio_set_bit(gpio2, ODR, pin, 1);
+ gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN);
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
+ reset(gpio2, IDR) & ~(1 << pin));
+
+ /* Trying to set a open-drain output pin, checking it doesn't work */
+ gpio_set_irq(gpio, pin, 1);
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
+
+ /* Trying to reset a open-drain output pin, checking it works */
+ gpio_set_bit(gpio, ODR, pin, 1);
+ gpio_set_irq(gpio, pin, 0);
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
+ reset(gpio2, IDR) & ~(1 << pin));
+
+ /* Clean the test */
+ disconnect_all_pins(gpio2);
+ gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER));
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR));
+ disconnect_all_pins(gpio);
+ gpio_writel(gpio, OTYPER, reset(gpio, OTYPER));
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
+}
+
+static void test_bsrr_brr(const void *data)
+{
+ /*
+ * Test that writing a '1' in BSS and BSRR
+ * has the desired effect on ODR.
+ * In BSRR, BSx has priority over BRx.
+ */
+ unsigned int pin = ((uint64_t)data) & 0xF;
+ uint32_t gpio = ((uint64_t)data) >> 32;
+
+ gpio_writel(gpio, BSRR, (1 << pin));
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
+
+ gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS)));
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
+
+ gpio_writel(gpio, BSRR, (1 << pin));
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
+
+ gpio_writel(gpio, BRR, (1 << pin));
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
+
+ /* BSx should have priority over BRx */
+ gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS)));
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
+
+ gpio_writel(gpio, BRR, (1 << pin));
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
+
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+ g_test_set_nonfatal_assertions();
+ qtest_add_func("stm32l4x5/gpio/test_idr_reset_value",
+ test_idr_reset_value);
+ /*
+ * The inputs for the tests (gpio and pin) can be changed,
+ * but the tests don't work for pins that are high at reset
+ * (GPIOA15, GPIO13 and GPIOB5).
+ * Specifically, rising the pin then checking `get_irq()`
+ * is problematic since the pin was already high.
+ */
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
+ (void *)((uint64_t)GPIO_C << 32 | 5),
+ test_gpio_output_mode);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
+ (void *)((uint64_t)GPIO_H << 32 | 3),
+ test_gpio_output_mode);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
+ (void *)((uint64_t)GPIO_D << 32 | 6),
+ test_gpio_input_mode);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
+ (void *)((uint64_t)GPIO_C << 32 | 10),
+ test_gpio_input_mode);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
+ (void *)((uint64_t)GPIO_B << 32 | 5),
+ test_pull_up_pull_down);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
+ (void *)((uint64_t)GPIO_F << 32 | 1),
+ test_pull_up_pull_down);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
+ (void *)((uint64_t)GPIO_G << 32 | 6),
+ test_push_pull);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
+ (void *)((uint64_t)GPIO_H << 32 | 3),
+ test_push_pull);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
+ (void *)((uint64_t)GPIO_C << 32 | 4),
+ test_open_drain);
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
+ (void *)((uint64_t)GPIO_E << 32 | 11),
+ test_open_drain);
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
+ (void *)((uint64_t)GPIO_A << 32 | 12),
+ test_bsrr_brr);
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
+ (void *)((uint64_t)GPIO_D << 32 | 0),
+ test_bsrr_brr);
+
+ qtest_start("-machine b-l475e-iot01a");
+ ret = g_test_run();
+ qtest_end();
+
+ return ret;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index cded1d0..ea3e232 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -67,7 +67,7 @@
# SME Tests
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
-AARCH64_TESTS += sme-outprod1
+AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
endif
# System Registers Tests
diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c
new file mode 100644
index 0000000..c62d5e0
--- /dev/null
+++ b/tests/tcg/aarch64/sme-smopa-1.c
@@ -0,0 +1,47 @@
+#include <stdio.h>
+#include <string.h>
+
+int main()
+{
+ static const int cmp[4][4] = {
+ { 110, 134, 158, 182 },
+ { 390, 478, 566, 654 },
+ { 670, 822, 974, 1126 },
+ { 950, 1166, 1382, 1598 }
+ };
+ int dst[4][4];
+ int *tmp = &dst[0][0];
+
+ asm volatile(
+ ".arch armv8-r+sme\n\t"
+ "smstart\n\t"
+ "index z0.b, #0, #1\n\t"
+ "movprfx z1, z0\n\t"
+ "add z1.b, z1.b, #16\n\t"
+ "ptrue p0.b\n\t"
+ "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t"
+ "ptrue p0.s, vl4\n\t"
+ "mov w12, #0\n\t"
+ "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t"
+ "smstop"
+ : "+r"(tmp) : : "memory");
+
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
+ return 0;
+ }
+
+ /* See above for correct results. */
+ for (int i = 0; i < 4; ++i) {
+ for (int j = 0; j < 4; ++j) {
+ printf("%6d", dst[i][j]);
+ }
+ printf("\n");
+ }
+ return 1;
+}
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
new file mode 100644
index 0000000..c9f48c3
--- /dev/null
+++ b/tests/tcg/aarch64/sme-smopa-2.c
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include <string.h>
+
+int main()
+{
+ static const long cmp[4][4] = {
+ { 110, 134, 158, 182 },
+ { 390, 478, 566, 654 },
+ { 670, 822, 974, 1126 },
+ { 950, 1166, 1382, 1598 }
+ };
+ long dst[4][4];
+ long *tmp = &dst[0][0];
+ long svl;
+
+ /* Validate that we have a wide enough vector for 4 elements. */
+ asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
+ if (svl < 32) {
+ return 0;
+ }
+
+ asm volatile(
+ "smstart\n\t"
+ "index z0.h, #0, #1\n\t"
+ "movprfx z1, z0\n\t"
+ "add z1.h, z1.h, #16\n\t"
+ "ptrue p0.b\n\t"
+ "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
+ "ptrue p0.d, vl4\n\t"
+ "mov w12, #0\n\t"
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
+ "add %0, %0, #32\n\t"
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
+ "mov w12, #2\n\t"
+ "add %0, %0, #32\n\t"
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
+ "add %0, %0, #32\n\t"
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
+ "smstop"
+ : "+r"(tmp) : : "memory");
+
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
+ return 0;
+ }
+
+ /* See above for correct results. */
+ for (int i = 0; i < 4; ++i) {
+ for (int j = 0; j < 4; ++j) {
+ printf("%6ld", dst[i][j]);
+ }
+ printf("\n");
+ }
+ return 1;
+}
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
index a7e390c..4da5b9a 100644
--- a/tests/tcg/riscv64/Makefile.target
+++ b/tests/tcg/riscv64/Makefile.target
@@ -17,4 +17,4 @@
TESTS += test-fcvtmod
test-fcvtmod: CFLAGS += -march=rv64imafdc
test-fcvtmod: LDFLAGS += -static
-run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,Zfa=true
+run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,zfa=true
diff --git a/ui/cocoa.m b/ui/cocoa.m
index eb99064..fa879d7 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -54,6 +54,10 @@
#define MAC_OS_X_VERSION_10_13 101300
#endif
+#ifndef MAC_OS_VERSION_14_0
+#define MAC_OS_VERSION_14_0 140000
+#endif
+
/* 10.14 deprecates NSOnState and NSOffState in favor of
* NSControlStateValueOn/Off, which were introduced in 10.13.
* Define for older versions
@@ -89,7 +93,6 @@
static void cocoa_refresh(DisplayChangeListener *dcl);
-static NSWindow *normalWindow;
static const DisplayChangeListenerOps dcl_ops = {
.dpy_name = "cocoa",
.dpy_gfx_update = cocoa_update,
@@ -99,12 +102,11 @@
static DisplayChangeListener dcl = {
.ops = &dcl_ops,
};
-static int last_buttons;
static int cursor_hide = 1;
static int left_command_key_enabled = 1;
static bool swap_opt_cmd;
-static bool stretch_video;
+static CGInterpolationQuality zoom_interpolation = kCGInterpolationNone;
static NSTextField *pauseLabel;
static bool allow_events;
@@ -304,20 +306,17 @@
*/
@interface QemuCocoaView : NSView
{
+ NSTrackingArea *trackingArea;
QEMUScreen screen;
- NSWindow *fullScreenWindow;
- float cx,cy,cw,ch,cdx,cdy;
pixman_image_t *pixman_image;
QKbdState *kbd;
BOOL isMouseGrabbed;
- BOOL isFullscreen;
BOOL isAbsoluteEnabled;
CFMachPortRef eventsTap;
}
- (void) switchSurface:(pixman_image_t *)image;
- (void) grabMouse;
- (void) ungrabMouse;
-- (void) toggleFullScreen:(id)sender;
- (void) setFullGrab:(id)sender;
- (void) handleMonitorInput:(NSEvent *)event;
- (bool) handleEvent:(NSEvent *)event;
@@ -333,8 +332,6 @@
*/
- (BOOL) isMouseGrabbed;
- (BOOL) isAbsoluteEnabled;
-- (float) cdx;
-- (float) cdy;
- (QEMUScreen) gscreen;
- (void) raiseAllKeys;
@end
@@ -365,6 +362,9 @@
screen.width = frameRect.size.width;
screen.height = frameRect.size.height;
kbd = qkbd_state_init(dcl.con);
+#if MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_14_0
+ [self setClipsToBounds:YES];
+#endif
}
return self;
@@ -392,46 +392,43 @@
return YES;
}
-- (BOOL) screenContainsPoint:(NSPoint) p
+- (void) removeTrackingRect
{
- return (p.x > -1 && p.x < screen.width && p.y > -1 && p.y < screen.height);
+ if (trackingArea) {
+ [self removeTrackingArea:trackingArea];
+ [trackingArea release];
+ trackingArea = nil;
+ }
}
-/* Get location of event and convert to virtual screen coordinate */
-- (CGPoint) screenLocationOfEvent:(NSEvent *)ev
+- (void) frameUpdated
{
- NSWindow *eventWindow = [ev window];
- // XXX: Use CGRect and -convertRectFromScreen: to support macOS 10.10
- CGRect r = CGRectZero;
- r.origin = [ev locationInWindow];
- if (!eventWindow) {
- if (!isFullscreen) {
- return [[self window] convertRectFromScreen:r].origin;
- } else {
- CGPoint locationInSelfWindow = [[self window] convertRectFromScreen:r].origin;
- CGPoint loc = [self convertPoint:locationInSelfWindow fromView:nil];
- if (stretch_video) {
- loc.x /= cdx;
- loc.y /= cdy;
- }
- return loc;
- }
- } else if ([[self window] isEqual:eventWindow]) {
- if (!isFullscreen) {
- return r.origin;
- } else {
- CGPoint loc = [self convertPoint:r.origin fromView:nil];
- if (stretch_video) {
- loc.x /= cdx;
- loc.y /= cdy;
- }
- return loc;
- }
- } else {
- return [[self window] convertRectFromScreen:[eventWindow convertRectToScreen:r]].origin;
+ [self removeTrackingRect];
+
+ if ([self window]) {
+ NSTrackingAreaOptions options = NSTrackingActiveInKeyWindow |
+ NSTrackingMouseEnteredAndExited |
+ NSTrackingMouseMoved;
+ trackingArea = [[NSTrackingArea alloc] initWithRect:[self frame]
+ options:options
+ owner:self
+ userInfo:nil];
+ [self addTrackingArea:trackingArea];
+ [self updateUIInfo];
}
}
+- (void) viewDidMoveToWindow
+{
+ [self resizeWindow];
+ [self frameUpdated];
+}
+
+- (void) viewWillMoveToWindow:(NSWindow *)newWindow
+{
+ [self removeTrackingRect];
+}
+
- (void) hideCursor
{
if (!cursor_hide) {
@@ -455,7 +452,7 @@
// get CoreGraphic context
CGContextRef viewContextRef = [[NSGraphicsContext currentContext] CGContext];
- CGContextSetInterpolationQuality (viewContextRef, kCGInterpolationNone);
+ CGContextSetInterpolationQuality (viewContextRef, zoom_interpolation);
CGContextSetShouldAntialias (viewContextRef, NO);
// draw screen bitmap directly to Core Graphics context
@@ -497,10 +494,8 @@
[self getRectsBeingDrawn:&rectList count:&rectCount];
for (i = 0; i < rectCount; i++) {
- clipRect.origin.x = rectList[i].origin.x / cdx;
- clipRect.origin.y = (float)h - (rectList[i].origin.y + rectList[i].size.height) / cdy;
- clipRect.size.width = rectList[i].size.width / cdx;
- clipRect.size.height = rectList[i].size.height / cdy;
+ clipRect = rectList[i];
+ clipRect.origin.y = (float)h - (clipRect.origin.y + clipRect.size.height);
clipImageRef = CGImageCreateWithImageInRect(
imageRef,
clipRect
@@ -513,39 +508,33 @@
}
}
-- (void) setContentDimensions
+- (NSSize) screenSafeAreaSize
{
- COCOA_DEBUG("QemuCocoaView: setContentDimensions\n");
+ NSSize size = [[[self window] screen] frame].size;
+ NSEdgeInsets insets = [[[self window] screen] safeAreaInsets];
+ size.width -= insets.left + insets.right;
+ size.height -= insets.top + insets.bottom;
+ return size;
+}
- if (isFullscreen) {
- cdx = [[NSScreen mainScreen] frame].size.width / (float)screen.width;
- cdy = [[NSScreen mainScreen] frame].size.height / (float)screen.height;
+- (void) resizeWindow
+{
+ [[self window] setContentAspectRatio:NSMakeSize(screen.width, screen.height)];
- /* stretches video, but keeps same aspect ratio */
- if (stretch_video == true) {
- /* use smallest stretch value - prevents clipping on sides */
- if (MIN(cdx, cdy) == cdx) {
- cdy = cdx;
- } else {
- cdx = cdy;
- }
- } else { /* No stretching */
- cdx = cdy = 1;
- }
- cw = screen.width * cdx;
- ch = screen.height * cdy;
- cx = ([[NSScreen mainScreen] frame].size.width - cw) / 2.0;
- cy = ([[NSScreen mainScreen] frame].size.height - ch) / 2.0;
- } else {
- cx = 0;
- cy = 0;
- cw = screen.width;
- ch = screen.height;
- cdx = 1.0;
- cdy = 1.0;
+ if (!([[self window] styleMask] & NSWindowStyleMaskResizable)) {
+ [[self window] setContentSize:NSMakeSize(screen.width, screen.height)];
+ [[self window] center];
+ } else if ([[self window] styleMask] & NSWindowStyleMaskFullScreen) {
+ [[self window] setContentSize:[self screenSafeAreaSize]];
+ [[self window] center];
}
}
+- (void) updateBounds
+{
+ [self setBoundsSize:NSMakeSize(screen.width, screen.height)];
+}
+
- (void) updateUIInfoLocked
{
/* Must be called with the BQL, i.e. via updateUIInfo */
@@ -561,9 +550,10 @@
CGDirectDisplayID display = [[description objectForKey:@"NSScreenNumber"] unsignedIntValue];
NSSize screenSize = [[[self window] screen] frame].size;
CGSize screenPhysicalSize = CGDisplayScreenSize(display);
+ bool isFullscreen = ([[self window] styleMask] & NSWindowStyleMaskFullScreen) != 0;
CVDisplayLinkRef displayLink;
- frameSize = isFullscreen ? screenSize : [self frame].size;
+ frameSize = isFullscreen ? [self screenSafeAreaSize] : [self frame].size;
if (!CVDisplayLinkCreateWithCGDisplay(display, &displayLink)) {
CVTime period = CVDisplayLinkGetNominalOutputVideoRefreshPeriod(displayLink);
@@ -610,31 +600,20 @@
});
}
-- (void)viewDidMoveToWindow
-{
- [self updateUIInfo];
-}
-
- (void) switchSurface:(pixman_image_t *)image
{
COCOA_DEBUG("QemuCocoaView: switchSurface\n");
int w = pixman_image_get_width(image);
int h = pixman_image_get_height(image);
- /* cdx == 0 means this is our very first surface, in which case we need
- * to recalculate the content dimensions even if it happens to be the size
- * of the initial empty window.
- */
- bool isResize = (w != screen.width || h != screen.height || cdx == 0.0);
- int oldh = screen.height;
- if (isResize) {
+ if (w != screen.width || h != screen.height) {
// Resize before we trigger the redraw, or we'll redraw at the wrong size
COCOA_DEBUG("switchSurface: new size %d x %d\n", w, h);
screen.width = w;
screen.height = h;
- [self setContentDimensions];
- [self setFrame:NSMakeRect(cx, cy, cw, ch)];
+ [self resizeWindow];
+ [self updateBounds];
}
// update screenBuffer
@@ -643,51 +622,6 @@
}
pixman_image = image;
-
- // update windows
- if (isFullscreen) {
- [[fullScreenWindow contentView] setFrame:[[NSScreen mainScreen] frame]];
- [normalWindow setFrame:NSMakeRect([normalWindow frame].origin.x, [normalWindow frame].origin.y - h + oldh, w, h + [normalWindow frame].size.height - oldh) display:NO animate:NO];
- } else {
- if (qemu_name)
- [normalWindow setTitle:[NSString stringWithFormat:@"QEMU %s", qemu_name]];
- [normalWindow setFrame:NSMakeRect([normalWindow frame].origin.x, [normalWindow frame].origin.y - h + oldh, w, h + [normalWindow frame].size.height - oldh) display:YES animate:NO];
- }
-
- if (isResize) {
- [normalWindow center];
- }
-}
-
-- (void) toggleFullScreen:(id)sender
-{
- COCOA_DEBUG("QemuCocoaView: toggleFullScreen\n");
-
- if (isFullscreen) { // switch from fullscreen to desktop
- isFullscreen = FALSE;
- [self ungrabMouse];
- [self setContentDimensions];
- [fullScreenWindow close];
- [normalWindow setContentView: self];
- [normalWindow makeKeyAndOrderFront: self];
- [NSMenu setMenuBarVisible:YES];
- } else { // switch from desktop to fullscreen
- isFullscreen = TRUE;
- [normalWindow orderOut: nil]; /* Hide the window */
- [self grabMouse];
- [self setContentDimensions];
- [NSMenu setMenuBarVisible:NO];
- fullScreenWindow = [[NSWindow alloc] initWithContentRect:[[NSScreen mainScreen] frame]
- styleMask:NSWindowStyleMaskBorderless
- backing:NSBackingStoreBuffered
- defer:NO];
- [fullScreenWindow setAcceptsMouseMovedEvents: YES];
- [fullScreenWindow setHasShadow:NO];
- [fullScreenWindow setBackgroundColor: [NSColor blackColor]];
- [self setFrame:NSMakeRect(cx, cy, cw, ch)];
- [[fullScreenWindow contentView] addSubview: self];
- [fullScreenWindow makeKeyAndOrderFront:self];
- }
}
- (void) setFullGrab:(id)sender
@@ -799,11 +733,8 @@
{
/* Return true if we handled the event, false if it should be given to OSX */
COCOA_DEBUG("QemuCocoaView: handleEvent\n");
- int buttons = 0;
+ InputButton button;
int keycode = 0;
- bool mouse_event = false;
- // Location of event in virtual screen coordinates
- NSPoint p = [self screenLocationOfEvent:event];
NSUInteger modifiers = [event modifierFlags];
/*
@@ -947,7 +878,7 @@
}
break;
}
- break;
+ return true;
case NSEventTypeKeyDown:
keycode = cocoa_keycode_to_qemu([event keyCode]);
@@ -983,7 +914,7 @@
} else {
[self handleMonitorInput: event];
}
- break;
+ return true;
case NSEventTypeKeyUp:
keycode = cocoa_keycode_to_qemu([event keyCode]);
@@ -996,153 +927,151 @@
if (qemu_console_is_graphic(NULL)) {
qkbd_state_key_event(kbd, keycode, false);
}
- break;
- case NSEventTypeMouseMoved:
- if (isAbsoluteEnabled) {
- // Cursor re-entered into a window might generate events bound to screen coordinates
- // and `nil` window property, and in full screen mode, current window might not be
- // key window, where event location alone should suffice.
- if (![self screenContainsPoint:p] || !([[self window] isKeyWindow] || isFullscreen)) {
- if (isMouseGrabbed) {
- [self ungrabMouse];
- }
- } else {
- if (!isMouseGrabbed) {
- [self grabMouse];
- }
- }
- }
- mouse_event = true;
- break;
- case NSEventTypeLeftMouseDown:
- buttons |= MOUSE_EVENT_LBUTTON;
- mouse_event = true;
- break;
- case NSEventTypeRightMouseDown:
- buttons |= MOUSE_EVENT_RBUTTON;
- mouse_event = true;
- break;
- case NSEventTypeOtherMouseDown:
- buttons |= MOUSE_EVENT_MBUTTON;
- mouse_event = true;
- break;
- case NSEventTypeLeftMouseDragged:
- buttons |= MOUSE_EVENT_LBUTTON;
- mouse_event = true;
- break;
- case NSEventTypeRightMouseDragged:
- buttons |= MOUSE_EVENT_RBUTTON;
- mouse_event = true;
- break;
- case NSEventTypeOtherMouseDragged:
- buttons |= MOUSE_EVENT_MBUTTON;
- mouse_event = true;
- break;
- case NSEventTypeLeftMouseUp:
- mouse_event = true;
- if (!isMouseGrabbed && [self screenContainsPoint:p]) {
- /*
- * In fullscreen mode, the window of cocoaView may not be the
- * key window, therefore the position relative to the virtual
- * screen alone will be sufficient.
- */
- if(isFullscreen || [[self window] isKeyWindow]) {
- [self grabMouse];
- }
- }
- break;
- case NSEventTypeRightMouseUp:
- mouse_event = true;
- break;
- case NSEventTypeOtherMouseUp:
- mouse_event = true;
- break;
+ return true;
case NSEventTypeScrollWheel:
/*
* Send wheel events to the guest regardless of window focus.
* This is in-line with standard Mac OS X UI behaviour.
*/
- /*
- * We shouldn't have got a scroll event when deltaY and delta Y
- * are zero, hence no harm in dropping the event
- */
- if ([event deltaY] != 0 || [event deltaX] != 0) {
/* Determine if this is a scroll up or scroll down event */
- if ([event deltaY] != 0) {
- buttons = ([event deltaY] > 0) ?
+ if ([event deltaY] != 0) {
+ button = ([event deltaY] > 0) ?
INPUT_BUTTON_WHEEL_UP : INPUT_BUTTON_WHEEL_DOWN;
- } else if ([event deltaX] != 0) {
- buttons = ([event deltaX] > 0) ?
+ } else if ([event deltaX] != 0) {
+ button = ([event deltaX] > 0) ?
INPUT_BUTTON_WHEEL_LEFT : INPUT_BUTTON_WHEEL_RIGHT;
- }
-
- qemu_input_queue_btn(dcl.con, buttons, true);
- qemu_input_event_sync();
- qemu_input_queue_btn(dcl.con, buttons, false);
- qemu_input_event_sync();
+ } else {
+ /*
+ * We shouldn't have got a scroll event when deltaY and delta Y
+ * are zero, hence no harm in dropping the event
+ */
+ return true;
}
- /*
- * Since deltaX/deltaY also report scroll wheel events we prevent mouse
- * movement code from executing.
- */
- mouse_event = false;
- break;
+ qemu_input_queue_btn(dcl.con, button, true);
+ qemu_input_event_sync();
+ qemu_input_queue_btn(dcl.con, button, false);
+ qemu_input_event_sync();
+
+ return true;
default:
return false;
}
+}
- if (mouse_event) {
- /* Don't send button events to the guest unless we've got a
- * mouse grab or window focus. If we have neither then this event
- * is the user clicking on the background window to activate and
- * bring us to the front, which will be done by the sendEvent
- * call below. We definitely don't want to pass that click through
- * to the guest.
- */
- if ((isMouseGrabbed || [[self window] isKeyWindow]) &&
- (last_buttons != buttons)) {
- static uint32_t bmap[INPUT_BUTTON__MAX] = {
- [INPUT_BUTTON_LEFT] = MOUSE_EVENT_LBUTTON,
- [INPUT_BUTTON_MIDDLE] = MOUSE_EVENT_MBUTTON,
- [INPUT_BUTTON_RIGHT] = MOUSE_EVENT_RBUTTON
- };
- qemu_input_update_buttons(dcl.con, bmap, last_buttons, buttons);
- last_buttons = buttons;
- }
- if (isMouseGrabbed) {
- if (isAbsoluteEnabled) {
- /* Note that the origin for Cocoa mouse coords is bottom left, not top left.
- * The check on screenContainsPoint is to avoid sending out of range values for
- * clicks in the titlebar.
- */
- if ([self screenContainsPoint:p]) {
- qemu_input_queue_abs(dcl.con, INPUT_AXIS_X, p.x, 0, screen.width);
- qemu_input_queue_abs(dcl.con, INPUT_AXIS_Y, screen.height - p.y, 0, screen.height);
- }
- } else {
- qemu_input_queue_rel(dcl.con, INPUT_AXIS_X, (int)[event deltaX]);
- qemu_input_queue_rel(dcl.con, INPUT_AXIS_Y, (int)[event deltaY]);
- }
- } else {
- return false;
- }
- qemu_input_event_sync();
+- (void) handleMouseEvent:(NSEvent *)event button:(InputButton)button down:(bool)down
+{
+ if (!isMouseGrabbed) {
+ return;
}
- return true;
+
+ with_bql(^{
+ qemu_input_queue_btn(dcl.con, button, down);
+ });
+
+ [self handleMouseEvent:event];
+}
+
+- (void) handleMouseEvent:(NSEvent *)event
+{
+ if (!isMouseGrabbed) {
+ return;
+ }
+
+ with_bql(^{
+ if (isAbsoluteEnabled) {
+ CGFloat d = (CGFloat)screen.height / [self frame].size.height;
+ NSPoint p = [event locationInWindow];
+
+ /* Note that the origin for Cocoa mouse coords is bottom left, not top left. */
+ qemu_input_queue_abs(dcl.con, INPUT_AXIS_X, p.x * d, 0, screen.width);
+ qemu_input_queue_abs(dcl.con, INPUT_AXIS_Y, screen.height - p.y * d, 0, screen.height);
+ } else {
+ qemu_input_queue_rel(dcl.con, INPUT_AXIS_X, [event deltaX]);
+ qemu_input_queue_rel(dcl.con, INPUT_AXIS_Y, [event deltaY]);
+ }
+
+ qemu_input_event_sync();
+ });
+}
+
+- (void) mouseExited:(NSEvent *)event
+{
+ if (isAbsoluteEnabled && isMouseGrabbed) {
+ [self ungrabMouse];
+ }
+}
+
+- (void) mouseEntered:(NSEvent *)event
+{
+ if (isAbsoluteEnabled && !isMouseGrabbed) {
+ [self grabMouse];
+ }
+}
+
+- (void) mouseMoved:(NSEvent *)event
+{
+ [self handleMouseEvent:event];
+}
+
+- (void) mouseDown:(NSEvent *)event
+{
+ [self handleMouseEvent:event button:INPUT_BUTTON_LEFT down:true];
+}
+
+- (void) rightMouseDown:(NSEvent *)event
+{
+ [self handleMouseEvent:event button:INPUT_BUTTON_RIGHT down:true];
+}
+
+- (void) otherMouseDown:(NSEvent *)event
+{
+ [self handleMouseEvent:event button:INPUT_BUTTON_MIDDLE down:true];
+}
+
+- (void) mouseDragged:(NSEvent *)event
+{
+ [self handleMouseEvent:event];
+}
+
+- (void) rightMouseDragged:(NSEvent *)event
+{
+ [self handleMouseEvent:event];
+}
+
+- (void) otherMouseDragged:(NSEvent *)event
+{
+ [self handleMouseEvent:event];
+}
+
+- (void) mouseUp:(NSEvent *)event
+{
+ if (!isMouseGrabbed) {
+ [self grabMouse];
+ }
+
+ [self handleMouseEvent:event button:INPUT_BUTTON_LEFT down:false];
+}
+
+- (void) rightMouseUp:(NSEvent *)event
+{
+ [self handleMouseEvent:event button:INPUT_BUTTON_RIGHT down:false];
+}
+
+- (void) otherMouseUp:(NSEvent *)event
+{
+ [self handleMouseEvent:event button:INPUT_BUTTON_MIDDLE down:false];
}
- (void) grabMouse
{
COCOA_DEBUG("QemuCocoaView: grabMouse\n");
- if (!isFullscreen) {
- if (qemu_name)
- [normalWindow setTitle:[NSString stringWithFormat:@"QEMU %s - (Press " UC_CTRL_KEY " " UC_ALT_KEY " G to release Mouse)", qemu_name]];
- else
- [normalWindow setTitle:@"QEMU - (Press " UC_CTRL_KEY " " UC_ALT_KEY " G to release Mouse)"];
- }
+ if (qemu_name)
+ [[self window] setTitle:[NSString stringWithFormat:@"QEMU %s - (Press " UC_CTRL_KEY " " UC_ALT_KEY " G to release Mouse)", qemu_name]];
+ else
+ [[self window] setTitle:@"QEMU - (Press " UC_CTRL_KEY " " UC_ALT_KEY " G to release Mouse)"];
[self hideCursor];
CGAssociateMouseAndMouseCursorPosition(isAbsoluteEnabled);
isMouseGrabbed = TRUE; // while isMouseGrabbed = TRUE, QemuCocoaApp sends all events to [cocoaView handleEvent:]
@@ -1152,15 +1081,14 @@
{
COCOA_DEBUG("QemuCocoaView: ungrabMouse\n");
- if (!isFullscreen) {
- if (qemu_name)
- [normalWindow setTitle:[NSString stringWithFormat:@"QEMU %s", qemu_name]];
- else
- [normalWindow setTitle:@"QEMU"];
- }
+ if (qemu_name)
+ [[self window] setTitle:[NSString stringWithFormat:@"QEMU %s", qemu_name]];
+ else
+ [[self window] setTitle:@"QEMU"];
[self unhideCursor];
CGAssociateMouseAndMouseCursorPosition(TRUE);
isMouseGrabbed = FALSE;
+ [self raiseAllButtons];
}
- (void) setAbsoluteEnabled:(BOOL)tIsAbsoluteEnabled {
@@ -1171,8 +1099,6 @@
}
- (BOOL) isMouseGrabbed {return isMouseGrabbed;}
- (BOOL) isAbsoluteEnabled {return isAbsoluteEnabled;}
-- (float) cdx {return cdx;}
-- (float) cdy {return cdy;}
- (QEMUScreen) gscreen {return screen;}
/*
@@ -1186,6 +1112,15 @@
qkbd_state_lift_all_keys(kbd);
});
}
+
+- (void) raiseAllButtons
+{
+ with_bql(^{
+ qemu_input_queue_btn(dcl.con, INPUT_BUTTON_LEFT, false);
+ qemu_input_queue_btn(dcl.con, INPUT_BUTTON_RIGHT, false);
+ qemu_input_queue_btn(dcl.con, INPUT_BUTTON_MIDDLE, false);
+ });
+}
@end
@@ -1200,7 +1135,6 @@
{
}
- (void)doToggleFullScreen:(id)sender;
-- (void)toggleFullScreen:(id)sender;
- (void)showQEMUDoc:(id)sender;
- (void)zoomToFit:(id) sender;
- (void)displayConsole:(id)sender;
@@ -1221,6 +1155,8 @@
@implementation QemuCocoaAppController
- (id) init
{
+ NSWindow *window;
+
COCOA_DEBUG("QemuCocoaAppController: init\n");
self = [super init];
@@ -1234,19 +1170,20 @@
}
// create a window
- normalWindow = [[NSWindow alloc] initWithContentRect:[cocoaView frame]
+ window = [[NSWindow alloc] initWithContentRect:[cocoaView frame]
styleMask:NSWindowStyleMaskTitled|NSWindowStyleMaskMiniaturizable|NSWindowStyleMaskClosable
backing:NSBackingStoreBuffered defer:NO];
- if(!normalWindow) {
+ if(!window) {
error_report("(cocoa) can't create window");
exit(1);
}
- [normalWindow setAcceptsMouseMovedEvents:YES];
- [normalWindow setTitle:@"QEMU"];
- [normalWindow setContentView:cocoaView];
- [normalWindow makeKeyAndOrderFront:self];
- [normalWindow center];
- [normalWindow setDelegate: self];
+ [window setAcceptsMouseMovedEvents:YES];
+ [window setCollectionBehavior:NSWindowCollectionBehaviorFullScreenPrimary];
+ [window setTitle:qemu_name ? [NSString stringWithFormat:@"QEMU %s", qemu_name] : @"QEMU"];
+ [window setContentView:cocoaView];
+ [window makeKeyAndOrderFront:self];
+ [window center];
+ [window setDelegate: self];
/* Used for displaying pause on the screen */
pauseLabel = [NSTextField new];
@@ -1312,9 +1249,21 @@
[cocoaView updateUIInfo];
}
+- (void)windowDidEnterFullScreen:(NSNotification *)notification
+{
+ [cocoaView grabMouse];
+}
+
+- (void)windowDidExitFullScreen:(NSNotification *)notification
+{
+ [cocoaView resizeWindow];
+ [cocoaView ungrabMouse];
+}
+
- (void)windowDidResize:(NSNotification *)notification
{
- [cocoaView updateUIInfo];
+ [cocoaView updateBounds];
+ [cocoaView frameUpdated];
}
/* Called when the user clicks on a window's close button */
@@ -1330,6 +1279,14 @@
return NO;
}
+- (NSApplicationPresentationOptions) window:(NSWindow *)window
+ willUseFullScreenPresentationOptions:(NSApplicationPresentationOptions)proposedOptions;
+
+{
+ return (proposedOptions & ~(NSApplicationPresentationAutoHideDock | NSApplicationPresentationAutoHideMenuBar)) |
+ NSApplicationPresentationHideDock | NSApplicationPresentationHideMenuBar;
+}
+
/*
* Called when QEMU goes into the background. Note that
* [-NSWindowDelegate windowDidResignKey:] is used here instead of
@@ -1349,14 +1306,7 @@
*/
- (void) doToggleFullScreen:(id)sender
{
- [self toggleFullScreen:(id)sender];
-}
-
-- (void)toggleFullScreen:(id)sender
-{
- COCOA_DEBUG("QemuCocoaAppController: toggleFullScreen\n");
-
- [cocoaView toggleFullScreen:sender];
+ [[cocoaView window] toggleFullScreen:sender];
}
- (void) setFullGrab:(id)sender
@@ -1403,10 +1353,19 @@
/* Stretches video to fit host monitor size */
- (void)zoomToFit:(id) sender
{
- stretch_video = !stretch_video;
- if (stretch_video == true) {
+ NSWindowStyleMask styleMask = [[cocoaView window] styleMask] ^ NSWindowStyleMaskResizable;
+
+ [[cocoaView window] setStyleMask:styleMask];
+ [sender setState:styleMask & NSWindowStyleMaskResizable ? NSControlStateValueOn : NSControlStateValueOff];
+}
+
+- (void)toggleZoomInterpolation:(id) sender
+{
+ if (zoom_interpolation == kCGInterpolationNone) {
+ zoom_interpolation = kCGInterpolationLow;
[sender setState: NSControlStateValueOn];
} else {
+ zoom_interpolation = kCGInterpolationNone;
[sender setState: NSControlStateValueOff];
}
}
@@ -1414,7 +1373,9 @@
/* Displays the console on the screen */
- (void)displayConsole:(id)sender
{
- console_select([sender tag]);
+ with_bql(^{
+ console_select([sender tag]);
+ });
}
/* Pause the guest */
@@ -1444,8 +1405,8 @@
{
/* Coordinates have to be calculated each time because the window can change its size */
int xCoord, yCoord, width, height;
- xCoord = ([normalWindow frame].size.width - [pauseLabel frame].size.width)/2;
- yCoord = [normalWindow frame].size.height - [pauseLabel frame].size.height - ([pauseLabel frame].size.height * .5);
+ xCoord = ([cocoaView frame].size.width - [pauseLabel frame].size.width)/2;
+ yCoord = [cocoaView frame].size.height - [pauseLabel frame].size.height - ([pauseLabel frame].size.height * .5);
width = [pauseLabel frame].size.width;
height = [pauseLabel frame].size.height;
[pauseLabel setFrame: NSMakeRect(xCoord, yCoord, width, height)];
@@ -1671,7 +1632,10 @@
menu = [[NSMenu alloc] initWithTitle:@"View"];
[menu addItem: [[[NSMenuItem alloc] initWithTitle:@"Enter Fullscreen" action:@selector(doToggleFullScreen:) keyEquivalent:@"f"] autorelease]]; // Fullscreen
menuItem = [[[NSMenuItem alloc] initWithTitle:@"Zoom To Fit" action:@selector(zoomToFit:) keyEquivalent:@""] autorelease];
- [menuItem setState: stretch_video ? NSControlStateValueOn : NSControlStateValueOff];
+ [menuItem setState: [[cocoaView window] styleMask] & NSWindowStyleMaskResizable ? NSControlStateValueOn : NSControlStateValueOff];
+ [menu addItem: menuItem];
+ menuItem = [[[NSMenuItem alloc] initWithTitle:@"Zoom Interpolation" action:@selector(toggleZoomInterpolation:) keyEquivalent:@""] autorelease];
+ [menuItem setState: zoom_interpolation == kCGInterpolationLow ? NSControlStateValueOn : NSControlStateValueOff];
[menu addItem: menuItem];
menuItem = [[[NSMenuItem alloc] initWithTitle:@"View" action:nil keyEquivalent:@""] autorelease];
[menuItem setSubmenu:menu];
@@ -1962,16 +1926,7 @@
COCOA_DEBUG("qemu_cocoa: cocoa_update\n");
dispatch_async(dispatch_get_main_queue(), ^{
- NSRect rect;
- if ([cocoaView cdx] == 1.0) {
- rect = NSMakeRect(x, [cocoaView gscreen].height - y - h, w, h);
- } else {
- rect = NSMakeRect(
- x * [cocoaView cdx],
- ([cocoaView gscreen].height - y - h) * [cocoaView cdy],
- w * [cocoaView cdx],
- h * [cocoaView cdy]);
- }
+ NSRect rect = NSMakeRect(x, [cocoaView gscreen].height - y - h, w, h);
[cocoaView setNeedsDisplayInRect:rect];
});
}
@@ -2048,8 +2003,7 @@
/* if fullscreen mode is to be used */
if (opts->has_full_screen && opts->full_screen) {
- [NSApp activateIgnoringOtherApps: YES];
- [controller toggleFullScreen: nil];
+ [[cocoaView window] toggleFullScreen: nil];
}
if (opts->u.cocoa.has_full_grab && opts->u.cocoa.full_grab) {
[controller setFullGrab: nil];
@@ -2067,7 +2021,11 @@
}
if (opts->u.cocoa.has_zoom_to_fit && opts->u.cocoa.zoom_to_fit) {
- stretch_video = true;
+ [cocoaView window].styleMask |= NSWindowStyleMaskResizable;
+ }
+
+ if (opts->u.cocoa.has_zoom_interpolation && opts->u.cocoa.zoom_interpolation) {
+ zoom_interpolation = kCGInterpolationLow;
}
create_initial_menus();
