commit | a84be2baa9eca8bc500f866ad943b8f63dc99adf | [log] [tgz] |
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author | Sergey Makarov <s.makarov@syntacore.com> | Wed Sep 18 17:02:29 2024 +0300 |
committer | Alistair Francis <alistair.francis@wdc.com> | Wed Oct 30 11:22:08 2024 +1000 |
tree | e6a973eab31b9f8099e0d6b7f890c524e5cc8e44 | |
parent | 41fc1f02947dd7a33b2c1d0e8474744b12f2514e [diff] |
hw/intc: Don't clear pending bits on IRQ lowering According to PLIC specification (chapter 5), there is only one case, when interrupt is claimed. Fix PLIC controller to match this behavior. Signed-off-by: Sergey Makarov <s.makarov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240918140229.124329-3-s.makarov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>