)]}'
{
  "commit": "f8a233dedf2560d7d592dab347ddf2a58e8a98db",
  "tree": "342ffe3d3450710555da2023ef1e31b7ef214a39",
  "parents": [
    "604d00c76fdd7dfcaa2bf8515615ad129a4fdcc4"
  ],
  "author": {
    "name": "Cédric Le Goater",
    "email": "clg@kaod.org",
    "time": "Wed Mar 02 06:51:38 2022 +0100"
  },
  "committer": {
    "name": "Cédric Le Goater",
    "email": "clg@kaod.org",
    "time": "Wed Mar 02 06:51:38 2022 +0100"
  },
  "message": "ppc/xive2: Introduce a XIVE2 core framework\n\nThe XIVE2 interrupt controller of the POWER10 processor as the same\nlogic as on POWER9 but its SW interface has been largely reworked. The\ninterrupt controller has a new register interface, different BARs,\nextra VSDs. These will be described when we add the device model for\nthe baremetal machine.\n\nThe XIVE internal structures for the EAS, END, NVT have different\nlayouts which is a problem for the current core XIVE framework. To\navoid adding too much complexity in the XIVE models, a new XIVE2 core\nframework is introduced. It duplicates the models which are closely\nlinked to the XIVE internal structures : Xive2Router and\nXive2ENDSource and reuses the XiveSource, XivePresenter, XiveTCTX\nmodels, as they are more generic.\n\nReviewed-by: Daniel Henrique Barboza \u003cdanielhb413@gmail.com\u003e\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\n",
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      "new_path": "hw/intc/meson.build"
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}