commit f7f5784af19155df658237d1aae04297d371402b
author Nikita Ostrenkov <n.ostrenkov@gmail.com> Mon Jan 08 14:32:58 2024 +0000
committer Peter Maydell <peter.maydell@linaro.org> Tue Jan 09 14:42:39 2024 +0000
tree fcdbe6fc81bd419969f8f45d3c89014f7772640a
parent 9468484fe904ab4691de6d9c34616667f377ceac

hw/arm: add cache controller for Freescale i.MX6

Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231219105510.4907-1-n.ostrenkov@gmail.com
[PMM: fixed stray whitespace]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

hw/arm/Kconfig

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 660f49d..b853577 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -537,6 +537,7 @@
     select IMX_I2C
     select IMX_USBPHY
     select WDT_IMX2
+    select PL310  # cache controller
     select SDHCI
 
 config ASPEED_SOC

hw/arm/fsl-imx6.c

diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index b215302..af2e982 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -154,6 +154,9 @@
                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
     }
 
+    /* L2 cache controller */
+    sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL);
+
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
         return;
     }