)]}'
{
  "commit": "f35f0f1ca121fb4931fe98570cda3aeb06b7a87f",
  "tree": "7eb911bf057f48051833ddb961bf40ba0ef89a2e",
  "parents": [
    "a7f27d6903b30bcea21c46986cb7507edcbc970c"
  ],
  "author": {
    "name": "liugan1",
    "email": "liugan1@lixiang.com",
    "time": "Tue May 05 09:25:21 2026 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue May 05 09:25:21 2026 +0100"
  },
  "message": "hw/intc/arm_gicv3: Fix NS write to ICC_AP1Rn_EL1 when prebits \u003c 7\n\nThe existing code uses a blanket `regno \u003c 2` check to make\nICC_AP1R0_EL1 and ICC_AP1R1_EL1 writes from Non-secure code WI\n(Write Ignore) when EL3 is present. This is intended to prevent\nNS code from claiming active interrupts in the Secure priority\nrange, which could block Secure interrupt delivery.\n\nHowever, that check assumes prebits\u003d7 (4 APR registers), where the\nNS priority range (128..255) maps entirely to AP1R2/AP1R3. Since\ncommit 39f29e599355 (\"hw/intc/arm_gicv3: Use correct number of\npriority bits for the CPU\", first in 7.1), all QEMU AArch64 CPUs\nare initialised with gic_pribits\u003d5 (one APR register), so NS\npriorities map to AP1R0 bits [16:31]. Blanket WI of the entire\nAP1R0 register prevents NS code from clearing its own NS active\npriority bits. Machines using hw_compat_7_0 (e.g. virt-7.0) still\nforce pribits\u003d8 via force-8-bit-prio and are therefore unaffected.\n\nA concrete consequence observed in virtualisation scenarios: when\na guest VM acknowledges an SPI interrupt but does not perform EOI,\nis force-killed and restarted, the new guest\u0027s attempt to clear\nthe residual active state by writing ICC_AP1R0_EL1\u003d0 is silently\nignored. The running priority (RPR) remains stuck at the old\ninterrupt\u0027s priority, preventing all equal-or-lower priority\ninterrupts (including timer interrupts) from being delivered, and\nhanging the guest.\n\nFix this by computing the exact Secure/NS boundary within the APR\nbank based on prebits. For registers entirely in the Secure range,\nkeep the WI behaviour. For the register that straddles the\nboundary, preserve only the Secure bits while allowing NS bits to\nbe modified. For registers entirely in the NS range, allow full\nwrite access.\n\nThe new logic produces identical behaviour to the old code when\nprebits\u003d7, preserving existing behaviour for machines that use\nforce-8-bit-prio.\n\nFixes: 39f29e599355 (\"hw/intc/arm_gicv3: Use correct number of priority bits for the CPU\")\nCc: qemu-stable@nongnu.org\nSigned-off-by: liugan1 \u003cliugan1@lixiang.com\u003e\nMessage-id: 20260428083119.1400110-1-gs_liugan@163.com\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fcb3922fa0f4e180b639a563f9b4522defbebf4e",
      "old_mode": 33188,
      "old_path": "hw/intc/arm_gicv3_cpuif.c",
      "new_id": "921d1fdfde47537b42f063a6566538fc025599a3",
      "new_mode": 33188,
      "new_path": "hw/intc/arm_gicv3_cpuif.c"
    }
  ]
}