Reorganize the CPUPPCState structure to group features.
Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3343 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 296727e..edff5cd 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -533,6 +533,7 @@
/* BATs 0-3 */
static void gen_low_BATs (CPUPPCState *env)
{
+#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_ibat, &spr_write_ibatu,
@@ -598,11 +599,13 @@
&spr_read_dbat, &spr_write_dbatl,
0x00000000);
env->nb_BATs += 4;
+#endif
}
/* BATs 4-7 */
static void gen_high_BATs (CPUPPCState *env)
{
+#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT4U, "IBAT4U",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_ibat_h, &spr_write_ibatu_h,
@@ -668,6 +671,7 @@
&spr_read_dbat_h, &spr_write_dbatl_h,
0x00000000);
env->nb_BATs += 4;
+#endif
}
/* Generic PowerPC time base */
@@ -694,6 +698,7 @@
/* Softare table search registers */
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
{
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
env->nb_ways = nb_ways;
env->id_tlbs = 1;
@@ -725,6 +730,7 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+#endif
}
/* SPR common to MPC755 and G2 */
@@ -1105,6 +1111,7 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_601_ubat, &spr_write_601_ubatu,
@@ -1138,6 +1145,7 @@
&spr_read_601_ubat, &spr_write_601_ubatl,
0x00000000);
env->nb_BATs = 4;
+#endif
}
static void gen_spr_74xx (CPUPPCState *env)
@@ -1238,6 +1246,7 @@
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
{
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
env->nb_ways = nb_ways;
env->id_tlbs = 1;
@@ -1256,6 +1265,7 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+#endif
}
/* PowerPC BookE SPR */
@@ -1512,6 +1522,7 @@
/* FSL storage control registers */
static void gen_spr_BookE_FSL (CPUPPCState *env)
{
+#if !defined(CONFIG_USER_ONLY)
/* TLB assist registers */
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_MAS0, "MAS0",
@@ -1605,6 +1616,7 @@
default:
break;
}
+#endif
}
/* SPR specific to PowerPC 440 implementation */
@@ -2616,9 +2628,11 @@
gen_spr_401x2(env);
gen_spr_compress(env);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2674,9 +2688,11 @@
gen_spr_401x2(env);
gen_spr_compress(env);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2744,9 +2760,11 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2785,9 +2803,11 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2832,9 +2852,11 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2860,9 +2882,11 @@
gen_spr_BookE(env);
gen_spr_440(env);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2889,9 +2913,11 @@
gen_spr_BookE(env);
gen_spr_440(env);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2935,9 +2961,11 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -2987,9 +3015,11 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3042,9 +3072,11 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3097,9 +3129,11 @@
gen_spr_BookE(env);
/* Memory management */
gen_spr_BookE_FSL(env);
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3167,10 +3201,11 @@
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
+#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
env->nb_ways = 2;
env->id_tlbs = 0;
- env->id_tlbs = 0;
+#endif
init_excp_601(env);
env->dcache_line_size = 64;
env->icache_line_size = 64;
@@ -4041,7 +4076,9 @@
#if !defined(CONFIG_USER_ONLY)
env->excp_prefix = 0xFFF00000;
#endif
+#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
+#endif
init_excp_970(env);
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -4112,7 +4149,9 @@
#if !defined(CONFIG_USER_ONLY)
env->excp_prefix = 0xFFF00000;
#endif
+#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
+#endif
init_excp_970(env);
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -4183,7 +4222,9 @@
#if !defined(CONFIG_USER_ONLY)
env->excp_prefix = 0xFFF00000;
#endif
+#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
+#endif
init_excp_970(env);
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -5729,11 +5770,11 @@
env->excp_prefix = 0x00000000;
env->ivor_mask = 0x00000000;
env->ivpr_mask = 0x00000000;
-#endif
/* Default MMU definitions */
env->nb_BATs = 0;
env->nb_tlb = 0;
env->nb_ways = 0;
+#endif
/* Register SPR common to all PowerPC implementations */
gen_spr_generic(env);
spr_register(env, SPR_PVR, "PVR",
@@ -5743,6 +5784,7 @@
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
(*def->init_proc)(env);
/* Allocate TLBs buffer when needed */
+#if !defined(CONFIG_USER_ONLY)
if (env->nb_tlb != 0) {
int nb_tlb = env->nb_tlb;
if (env->id_tlbs != 0)
@@ -5751,7 +5793,6 @@
/* Pre-compute some useful values */
env->tlb_per_way = env->nb_tlb / env->nb_ways;
}
-#if !defined(CONFIG_USER_ONLY)
if (env->irq_inputs == NULL) {
fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
" Attempt Qemu to crash very soon !\n");
@@ -6171,11 +6212,13 @@
printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
" MMU model : %s\n",
def->name, def->pvr, def->msr_mask, mmu_model);
+#if !defined(CONFIG_USER_ONLY)
if (env->tlb != NULL) {
printf(" %d %s TLB in %d ways\n",
env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
env->nb_ways);
}
+#endif
printf(" Exceptions model : %s\n"
" Bus model : %s\n",
excp_model, bus_model);
