tree 056255a6b9fbae70677f1de0a0382855f85f73e7
parent 2d2a4549cc29850aab891495685a7b31f5254b12
author Cédric Le Goater <clg@kaod.org> 1548066191 +0000
committer Peter Maydell <peter.maydell@linaro.org> 1548066191 +0000

ftgmac100: implement the new MDIO interface on Aspeed SoC

The PHY behind the MAC of an Aspeed SoC can be controlled using two
different MDC/MDIO interfaces. The same registers PHYCR (MAC60) and
PHYDATA (MAC64) are involved but they have a different layout.

BIT31 of the Feature Register (MAC40) controls which MDC/MDIO
interface is active.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190111125759.31577-1-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>