)]}'
{
  "commit": "f037f5b4b91a32bf8f1ec2c8ff92d2d14242adb4",
  "tree": "61f858d86ef739760e7168e772b7ff1d03ebeb6d",
  "parents": [
    "88c756bc9e5d38b6e46e631b9875ae954a319ed9"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Apr 26 13:29:13 2024 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue Apr 30 15:14:15 2024 +0100"
  },
  "message": "target/arm: Default to 1GHz cntfrq for \u0027max\u0027 and new CPUs\n\nIn previous versions of the Arm architecture, the frequency of the\ngeneric timers as reported in CNTFRQ_EL0 could be any IMPDEF value,\nand for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.\nIn Armv8.6, the architecture standardized this frequency to 1GHz.\n\nBecause there is no ID register feature field that indicates whether\na CPU is v8.6 or that it ought to have this counter frequency, we\nimplement this by changing our default CNTFRQ value for all CPUs,\nwith exceptions for backwards compatibility:\n\n * CPU types which we already implement will retain the old\n   default value. None of these are v8.6 CPUs, so this is\n   architecturally OK.\n * CPUs used in versioned machine types with a version of 9.0\n   or earlier will retain the old default value.\n\nThe upshot is that the only CPU type that changes is \u0027max\u0027; but any\nnew type we add in future (whether v8.6 or not) will also get the new\n1GHz default.\n\nIt remains the case that the machine model can override the default\nvalue via the \u0027cntfrq\u0027 QOM property (regardless of the CPU type).\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-id: 20240426122913.3427983-5-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0dec48e8021a44265a4313a79fcc8f9051b6b8f5",
      "old_mode": 33188,
      "old_path": "hw/core/machine.c",
      "new_id": "4ff60911e74cf0f4878a30d7c4934fb53c7ba4f1",
      "new_mode": 33188,
      "new_path": "hw/core/machine.c"
    },
    {
      "type": "modify",
      "old_id": "9f2ca6633a150870875d8b2b581fed0280c92d7f",
      "old_mode": 33188,
      "old_path": "target/arm/cpu.c",
      "new_id": "fdc3eda318a7ea27cf384d082a37807f548efc96",
      "new_mode": 33188,
      "new_path": "target/arm/cpu.c"
    },
    {
      "type": "modify",
      "old_id": "1f90590f937a4f20a7bef8ab05fa2831e27af85c",
      "old_mode": 33188,
      "old_path": "target/arm/cpu.h",
      "new_id": "a550bcd25fe7bb8403640bce36943eaef18add9a",
      "new_mode": 33188,
      "new_path": "target/arm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "985b1efe160a51e7b2bf2c1ad8968130a33c5143",
      "old_mode": 33188,
      "old_path": "target/arm/cpu64.c",
      "new_id": "c15d086049fda85213ecdc11a240aa272d536f0b",
      "new_mode": 33188,
      "new_path": "target/arm/cpu64.c"
    },
    {
      "type": "modify",
      "old_id": "b6c78db0243008aa691741a32ebf54ad6c5822c6",
      "old_mode": 33188,
      "old_path": "target/arm/internals.h",
      "new_id": "ee3ebd383e15dc33148393dc859ea9f56f80c2cb",
      "new_mode": 33188,
      "new_path": "target/arm/internals.h"
    },
    {
      "type": "modify",
      "old_id": "b5a60682fa61a7ddf5143b64298f017c2f602498",
      "old_mode": 33188,
      "old_path": "target/arm/tcg/cpu32.c",
      "new_id": "bdd82d912a22246c89e3528d4384c70b21c7578a",
      "new_mode": 33188,
      "new_path": "target/arm/tcg/cpu32.c"
    },
    {
      "type": "modify",
      "old_id": "443cffe3a857d0743aa6d4f60828374472a63251",
      "old_mode": 33188,
      "old_path": "target/arm/tcg/cpu64.c",
      "new_id": "da41a44f75b228517d600d4015071c519abf347b",
      "new_mode": 33188,
      "new_path": "target/arm/tcg/cpu64.c"
    }
  ]
}