)]}'
{
  "commit": "ee5bf0962ed6e0eb42d6bc9bfb3687f2408e3580",
  "tree": "c8062fbe595cbb5b0265bb9bc6e12854aabad652",
  "parents": [
    "05f32d2584f40462aff5468cd47919b4a9077b9a"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 18 18:40:13 2026 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 18 18:40:13 2026 +0000"
  },
  "message": "target/arm: Fix feature check in DO_SVE2_RRX, DO_SVE2_RRX_TB\n\nIn the macros DO_SVE2_RRX and DO_SVE2_RRX_TB we use the\nfeature check aa64_sve, thus exposing this set of instructions\nin SVE as well as SVE2. Use aa64_sve2 instead, so they UNDEF\non an SVE1-only CPU as they should.\n\nStrictly, the condition here should be \"SVE2 or SME\"; but we\nwill correct that in a following commit with all the other\nmissing \"or SME\" checks.\n\nCc: qemu-stable@nongnu.org\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Manos Pitsidianakis \u003cmanos.pitsidianakis@linaro.org\u003e\nMessage-id: 20260202133353.2231685-4-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "64adb5c1ce3c4e7a2f999e4c12dd04b2da3c2064",
      "old_mode": 33188,
      "old_path": "target/arm/tcg/translate-sve.c",
      "new_id": "81f487152ce9cdc79392318d89e88f9834582eba",
      "new_mode": 33188,
      "new_path": "target/arm/tcg/translate-sve.c"
    }
  ]
}