)]}'
{
  "commit": "ed9eb206942e31abbc593a4bfe8bb97f5fb5d551",
  "tree": "7e78004debb5b48d5cf28e637a3551a33049ba90",
  "parents": [
    "6df3747a2745534c86db8e8f2ffdb1b8a66e5e84"
  ],
  "author": {
    "name": "Alexandre Ghiti",
    "email": "alexghiti@rivosinc.com",
    "time": "Fri Mar 03 14:12:52 2023 +0100"
  },
  "committer": {
    "name": "Palmer Dabbelt",
    "email": "palmer@rivosinc.com",
    "time": "Mon Mar 06 08:09:44 2023 -0800"
  },
  "message": "riscv: Correctly set the device-tree entry \u0027mmu-type\u0027\n\nThe \u0027mmu-type\u0027 should reflect what the hardware is capable of so use the\nnew satp_mode field in RISCVCPUConfig to do that.\n\nSigned-off-by: Alexandre Ghiti \u003calexghiti@rivosinc.com\u003e\nReviewed-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nReviewed-by: Bin Meng \u003cbmeng@tinylab.org\u003e\nReviewed-by: Frank Chang \u003cfrank.chang@sifive.com\u003e\nMessage-ID: \u003c20230303131252.892893-6-alexghiti@rivosinc.com\u003e\nSigned-off-by: Palmer Dabbelt \u003cpalmer@rivosinc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7f70fa11a17af113b3cb84004cc8ae21df45d400",
      "old_mode": 33188,
      "old_path": "hw/riscv/virt.c",
      "new_id": "26eb81d03615298a77bedcefe51627f5d27995ff",
      "new_mode": 33188,
      "new_path": "hw/riscv/virt.c"
    }
  ]
}