)]}'
{
  "commit": "ed9b28fb009a7944fcda89c3ced3cb6ad4a92ea1",
  "tree": "5870619ebfc91af3ba84368fc308660259489804",
  "parents": [
    "3128588232333beb505505366133d18da671e2c8"
  ],
  "author": {
    "name": "Matheus Tavares Bernardino",
    "email": "quic_mathbern@quicinc.com",
    "time": "Thu May 11 09:36:01 2023 -0700"
  },
  "committer": {
    "name": "Taylor Simpson",
    "email": "tsimpson@quicinc.com",
    "time": "Thu May 18 12:40:52 2023 -0700"
  },
  "message": "Hexagon (iclass): update J4_hintjumpr slot constraints\n\nThe Hexagon PRM says that \"The assembler automatically encodes\ninstructions in the packet in the proper order. In the binary encoding\nof a packet, the instructions must be ordered from Slot 3 down to\nSlot 0.\"\n\nPrior to the architecture version v73, the slot constraints from\ninstruction \"hintjr\" only allowed it to be executed at slot 2.\nWith that in mind, consider the packet:\n\n    {\n        hintjr(r0)\n        nop\n        nop\n        if (!p0) memd(r1+#0) \u003d r1:0\n    }\n\nTo satisfy the ordering rule quoted from the PRM, the assembler would,\nthus, move one of the nops to the first position, so that it can be\nassigned to slot 3 and the subsequent hintjr to slot 2.\n\nHowever, since v73, hintjr can be executed at either slot 2 or 3. So\nthere is no need to reorder that packet and the assembler will encode it\nas is. When QEMU tries to execute it, however, we end up hitting a\n\"misaliged store\" exception because both the store and the hintjr will\nbe assigned to store 0, and some functions like `slot_is_predicated()`\nexpect the decode machinery to assign only one instruction per slot. In\nparticular, the mentioned function will traverse the packet until it\nfinds the first instruction at the desired slot which, for slot 0, will\nbe hintjr. Since hintjr is not predicated, the result is that we try to\nexecute the store regardless of the predicate. And because the predicate\nis false, we had not previously loaded hex_store_addr[0] or\nhex_store_width[0]. As a result, the store will decide de width based on\ntrash memory, causing it to be misaligned.\n\nUpdate the slot constraints for hintjr so that QEMU can properly handle\nsuch encodings.\n\nNote: to avoid similar-but-not-identical issues in the future, we should\nlook for multiple instructions at the same slot during decoding time and\nthrow an invalid packet exception. That will be done in the subsequent\ncommit.\n\nSigned-off-by: Matheus Tavares Bernardino \u003cquic_mathbern@quicinc.com\u003e\nReviewed-by: Taylor Simpson \u003ctsimpson@quicinc.com\u003e\nSigned-off-by: Taylor Simpson \u003ctsimpson@quicinc.com\u003e\nMessage-Id: \u003c0fcd8293642c6324119fbbab44741164bcbd04fb.1673616964.git.quic_mathbern@quicinc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6091286993570c2aed29013d00d0d5757a851a59",
      "old_mode": 33188,
      "old_path": "target/hexagon/iclass.c",
      "new_id": "c3f8523b27d597f90b5354f255c17bd6a496b006",
      "new_mode": 33188,
      "new_path": "target/hexagon/iclass.c"
    }
  ]
}