)]}'
{
  "commit": "ec08d9a51e6af3cd3edbdbf2ca6e97a1e2b5f0d1",
  "tree": "8ff6f0a345136b2a696e4c384c314d51e8a4b9e8",
  "parents": [
    "bdb468294135bf259ed0281d13b0ef5d989e1c9a",
    "99ec7b440a1d6a6ef07450b68687d24d13a25fb5"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Sep 06 13:59:37 2024 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Sep 06 13:59:37 2024 +0100"
  },
  "message": "Merge tag \u0027pull-target-arm-20240905\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm into staging\n\ntarget-arm queue:\n * Implement FEAT_EBF16 emulation\n * accel/tcg: Remove dead code from rr_cpu_thread_fn()\n * hw: add compat machines for 9.2\n * virt: default to two-stage SMMU from virt-9.2\n * sbsa-ref: use two-stage SMMU\n * hw: Various minor memory leak fixes\n * target/arm: Correct names of VFP VFNMA and VFNMS insns\n * hw/arm/xilinx_zynq: Enable Security Extensions\n * hw/arm/boot: Report error msg if loading elf/dtb failed\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmbZqzEZHHBldGVyLm1h\n# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lJ7D/9s/ZTkiCj/z+caHotwNJVt\n# ECgEEVinitwZxSMINZd1f6bxTY8hYVjMewj6A6RvHtMJMr7SUOmL8wi0YlbhTm44\n# jb8dZVf3pzPaZ399jxOeGnFipGyKmK0XM5rKc7CP6yJUS3B9RkUbLEHng8Q0ZBtl\n# cnZqI12jJBdtHU8D4JIvBgM2N2ay4bKY8EQEPCv4S7ZTKawWcKgSR5pMd2TBIqIT\n# 0gaDL3eOgCt2XWIrMzRjvaJK70obN/+n+vZQskJ/sIDsw+Kz8sZGlivdBXLRmQ+A\n# OUgtdyZoD42Q8KtwM0bjoaoxz6VMNPJp5khB45EPjVgWyeyJ0L6ZcWCX7nT4hZsi\n# 1C0NJaJU6HQbfsPiMIGxgHYJCbQue/mVBE02MPhmN8fZlsTRKWT9Miu67S0PI5Ib\n# ZWo88Ew1coucBm25K2NWdoR3dCP8EFnxqL556L8M4iDWYQ/djf8cpFAN9QJBFrNw\n# CaXS+vxIFUjZ6TSjf8gOYPAONmAg5DsCucgyO4MBKnvlY5h2J+GTq/FC+kWzL9jE\n# UfhqOWSP34ol2lg319zOtKg4Ga+GOivo2DmgWQhDwZ2rmRR+xgN8rkQjpJKIT5Zj\n# Ji+ucJrghBZ0sN622QYG0u0Ap9Jy4KCOxcFfS1b4gNhmMDWg27Tx9tIguXmjOE3M\n# aAs4wmm4Nz4kpsf1KkB11Q\u003d\u003d\n# \u003dgZuf\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Thu 05 Sep 2024 13:59:29 BST\n# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE\n# gpg:                issuer \"peter.maydell@linaro.org\"\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\" [ultimate]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@gmail.com\u003e\" [ultimate]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@chiark.greenend.org.uk\u003e\" [ultimate]\n# gpg:                 aka \"Peter Maydell \u003cpeter@archaic.org.uk\u003e\" [ultimate]\n# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE\n\n* tag \u0027pull-target-arm-20240905\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm: (25 commits)\n  platform-bus: fix refcount leak\n  hw/arm/boot: Explain why load_elf_hdr() error is ignored\n  hw/arm/boot: Report error msg if loading elf/dtb failed\n  hw/arm/xilinx_zynq: Enable Security Extensions\n  target/arm: Correct names of VFP VFNMA and VFNMS insns\n  hw/arm/sbsa-ref: Don\u0027t leak string in sbsa_fdt_add_gic_node()\n  hm/nvram/xlnx-versal-efuse-ctrl: Call register_finalize_block\n  hw/misc/xlnx-versal-trng: Call register_finalize_block\n  hw/nvram/xlnx-zynqmp-efuse: Call register_finalize_block\n  hw/nvram/xlnx-bbram: Call register_finalize_block\n  hw/misc/xlnx-versal-trng: Free s-\u003eprng in finalize, not unrealize\n  hw/misc/xlnx-versal-cfu: destroy fifo in finalize\n  hw/arm/sbsa-ref: Use two-stage SMMU\n  hw/arm/virt: Default to two-stage SMMU from virt-9.2\n  hw/arm/smmuv3: Update comment documenting \"stage\" property\n  hw: add compat machines for 9.2\n  accel/tcg: Remove dead code from rr_cpu_thread_fn()\n  target/arm: Enable FEAT_EBF16 in the \"max\" CPU\n  target/arm: Implement FPCR.EBF\u003d1 semantics for bfdotadd()\n  target/arm: Prepare bfdotadd() callers for FEAT_EBF support\n  ...\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}