commit | ebfdc4942810905c44a59ee92f3d3809f40ee253 | [log] [tgz] |
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author | Francisco Iglesias <francisco.iglesias@amd.com> | Thu Aug 31 17:56:56 2023 +0100 |
committer | Peter Maydell <peter.maydell@linaro.org> | Fri Sep 08 16:41:35 2023 +0100 |
tree | b82b42e4e242378a4aab1dc8dd4a964aa5463f74 | |
parent | 86d916c62145168120ec97a71404d91c0aa72835 [diff] |
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Introduce a model of Xilinx Versal's Configuration Frame Unit's data out port (CFU_FDRO). Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230831165701.2016397-4-francisco.iglesias@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>