)]}'
{
  "commit": "ea652c2beeaec51035f76aeb976af06858ee85ce",
  "tree": "98ede3a84dd09e3450b548f795703503ca75d636",
  "parents": [
    "1a2623b5c9e7cb6c9cc69dd4b467c9cbb1c98877"
  ],
  "author": {
    "name": "Tomita Moeko",
    "email": "tomitamoeko@gmail.com",
    "time": "Fri Dec 06 20:27:46 2024 +0800"
  },
  "committer": {
    "name": "Cédric Le Goater",
    "email": "clg@redhat.com",
    "time": "Thu Dec 26 07:23:37 2024 +0100"
  },
  "message": "vfio/igd: emulate GGC register in mmio bar0\n\nThe GGC register at 0x50 of pci config space is a mirror of the same\nregister at 0x108040 of mmio bar0 [1]. i915 driver also reads that\nregister from mmio bar0 instead of config space. As GGC is programmed\nand emulated by qemu, the mmio address should also be emulated, in the\nsame way of BDSM register.\n\n[1] 4.1.28, 12th Generation Intel Core Processors Datasheet Volume 2\n    https://www.intel.com/content/www/us/en/content-details/655259\n\nSigned-off-by: Tomita Moeko \u003ctomitamoeko@gmail.com\u003e\nReviewed-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nLink: https://lore.kernel.org/r/20241206122749.9893-9-tomitamoeko@gmail.com\nSigned-off-by: Cédric Le Goater \u003cclg@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4e93af1f8dc773e74f86dedfa34a93e511515875",
      "old_mode": 33188,
      "old_path": "hw/vfio/igd.c",
      "new_id": "828222cad13400034d12e748a982af275f21cda1",
      "new_mode": 33188,
      "new_path": "hw/vfio/igd.c"
    }
  ]
}