)]}'
{
  "commit": "ea3f0ebc1a3ba380e682ea8aad38f8e8cbc0d6f7",
  "tree": "fa68df32deeb7345e99f7c51e5592bab70bfac5d",
  "parents": [
    "6d1bda91337dcd0e7bf78da6f6b15af497966052"
  ],
  "author": {
    "name": "Jonathan Cameron",
    "email": "Jonathan.Cameron@huawei.com",
    "time": "Mon Sep 16 18:35:16 2024 +0100"
  },
  "committer": {
    "name": "Michael S. Tsirkin",
    "email": "mst@redhat.com",
    "time": "Mon Nov 04 16:03:24 2024 -0500"
  },
  "message": "hw/pcie: Provide a utility function for control of EP / SW USP link\n\nWhilst similar to existing PCIESlot link configuration a few registers\nneed to be set differently so that the downstream device presents\na \u0027configured\u0027 state that is then used to \u0027train\u0027 the upstream port\non the link.  Basically that means setting the status register to\nreflect it succeeding in training up to target settings.\n\nSigned-off-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nMessage-Id: \u003c20240916173518.1843023-5-Jonathan.Cameron@huawei.com\u003e\nReviewed-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1ac6d89dcfcad276538094f7204cf8a20a2517e3",
      "old_mode": 33188,
      "old_path": "hw/pci/pcie.c",
      "new_id": "2738dbb28d9ce60085e83ad8a6f14c570a49b6f9",
      "new_mode": 33188,
      "new_path": "hw/pci/pcie.c"
    },
    {
      "type": "modify",
      "old_id": "5eddb9097693fc0328df7589ec36fa03556c9283",
      "old_mode": 33188,
      "old_path": "include/hw/pci/pcie.h",
      "new_id": "b8d59732bc636971b0640e63f036c994a65db932",
      "new_mode": 33188,
      "new_path": "include/hw/pci/pcie.h"
    }
  ]
}