commit e9ebed4d41fc0630e433a32ecfd1057cae8b10bf
author blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Apr 22 19:14:52 2007 +0000
committer blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Apr 22 19:14:52 2007 +0000
tree f0b197365516014c503bfd86b4c9c86c0daa6777
parent 3d834c78b28ec08f857ce1fcbd2e962ad7b87740

Sparc64 update: more VIS ops


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2714 c046a42c-6fe2-441c-8c8c-71466251a162

target-sparc/cpu.h

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 50e162a..f3f872f 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -225,6 +225,9 @@
     uint64_t fprs;
     uint64_t tick_cmpr, stick_cmpr;
     uint64_t gsr;
+    uint32_t gl; // UA2005
+    /* UA 2005 hyperprivileged registers */
+    uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
 #endif
 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
     target_ulong t2;