)]}'
{
  "commit": "e8779f3d1509cd07620c6166a9a280376e01ff2f",
  "tree": "6cbbd6d5d7b75c3c6813ec11ca52d5721f612293",
  "parents": [
    "88b1716a407459c8189473e4667653cb8e4c3df7",
    "eccf20c02a5ad913a910444dc6bbe5de0952d254"
  ],
  "author": {
    "name": "Richard Henderson",
    "email": "richard.henderson@linaro.org",
    "time": "Fri Oct 24 10:53:02 2025 +0200"
  },
  "committer": {
    "name": "Richard Henderson",
    "email": "richard.henderson@linaro.org",
    "time": "Fri Oct 24 10:53:02 2025 +0200"
  },
  "message": "Merge tag \u0027pull-riscv-to-apply-20251024\u0027 of https://github.com/alistair23/qemu into staging\n\nSecond RISC-V PR for 10.2\n\n* Correct mmu-type property of sifive_u harts in device tree\n* Centralize MO_TE uses in a pair of helpers\n* Fix Ethernet interface support for microchip-icicle-kit\n* Fix mask for smsiaddrcfgh\n* Fix env-\u003epriv setting in reset_regs_csr()\n* Coverity-related fixes\n* Fix riscv_cpu_sirq_pending() mask\n* Fix a uninitialized variable warning\n* Make PMP granularity configurable\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmj6vn4ACgkQr3yVEwxT\n# gBORBg/9HMcPIWY4TweyZXcVkcB/4LY3XboBCcumTUO3dEkiVMYc5TDauO++YiyJ\n# YPRzFSAgwNxoF2ndtNLSc6OCu6LPRzWpt9a/MavTzfNLOQZ5vUbYCd3g24uR4Plz\n# AOt7Jn9l8+95MxGeTq5NfDdOnyC+mF4EiIjhplbZz7UcMpouKRysAibSjuyXlYGD\n# DutmQ/bctyDsASNFIl3xwT4po1M4EgMX4nL01ZbfYw2sTjPH2Vj53E0eQ9iZCsP6\n# l8L8PEz4Jiad2rapJdm2OS6mirMd3PZbYWqvRga/NQiTs4jGYSxiIhlpqR3Ez2id\n# UBGjLKcbsgvyaX1ILq3n6nfftjrXpSEnCMh86/H3xZ8dhA8eBMrGTJvYXAX33ao5\n# d3ClcT+E7FTduc+hWl/B/l3eb6fOcEIQ172slBiPEfJJqwJgkXgOfftlxRJQ3iGs\n# FbpCL0zEeB1/0SUvgI8Wv5652GiaAljWhhIM7FhWpohc2DxV2iUXuxhhXgHkztwL\n# EIddIo9FLQqY7wxlQhvQKRT0hCm/9mtokq6jiQUTuVMn7gf4fWdvDSozRvX1b0DB\n# CiJcPnKgM/M4UQHci8rboADWPSJ8oOSdz5dheQfXVNJczFnDqzMMVFbkFicXidJU\n# aT+1sPuuSYE6hquR1p4yvxeyyfIQCdffzRBr3WZ2iq7GQ+I4/64\u003d\n# \u003dP0/u\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Fri 24 Oct 2025 01:47:10 AM CEST\n# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013\n# gpg: Good signature from \"Alistair Francis \u003calistair@alistair23.me\u003e\" [unknown]\n# gpg: WARNING: This key is not certified with a trusted signature!\n# gpg:          There is no indication that the signature belongs to the owner.\n# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013\n\n* tag \u0027pull-riscv-to-apply-20251024\u0027 of https://github.com/alistair23/qemu: (25 commits)\n  target/riscv: Make PMP CSRs conform to WARL constraints\n  target/riscv: Make PMP granularity configurable\n  target/riscv: Fix a uninitialized variable warning\n  target/riscv: fix riscv_cpu_sirq_pending() mask\n  target/riscv/riscv-qmp-cmds.c: coverity-related fixes\n  target/riscv/kvm: fix env-\u003epriv setting in reset_regs_csr()\n  hw/intc: Allow gaps in hartids for aclint and aplic\n  aplic: fix mask for smsiaddrcfgh\n  microchip icicle: Enable PCS on Cadence Ethernet\n  hw/net/cadence_gem: Add pcs-enabled property\n  hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels\n  hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus\n  target/riscv: Introduce mo_endian_env() helper\n  target/riscv: Introduce mo_endian() helper\n  target/riscv: Factor MemOp variable out when MO_TE is set\n  target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc()\n  target/riscv: Conceal MO_TE within gen_cmpxchg*()\n  target/riscv: Conceal MO_TE within gen_storepair_tl()\n  target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()\n  target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx()\n  ...\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n",
  "tree_diff": []
}