commit e748ba4f5352061474668a47341abe2a898e03ad
author bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Nov 03 22:25:25 2003 +0000
committer bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Nov 03 22:25:25 2003 +0000
tree 0d2711dbb3b579eb7d0d30254e986c7b6f535799
parent b8ed223bfe3b1af434adce07b2981ce8b5b9ecb4

ARM half word load/store fix (Ulrich Hecht)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@438 c046a42c-6fe2-441c-8c8c-71466251a162

target-arm/translate.c

diff --git a/target-arm/translate.c b/target-arm/translate.c
index bffeefa..808fa2b 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -546,8 +546,7 @@
                 rn = (insn >> 16) & 0xf;
                 rd = (insn >> 12) & 0xf;
                 gen_movl_T1_reg(s, rn);
-                if (insn & (1 << 25))
-                    gen_add_datah_offset(s, insn);
+                gen_add_datah_offset(s, insn);
                 if (insn & (1 << 20)) {
                     /* load */
                     switch(sh) {
@@ -562,8 +561,10 @@
                         gen_op_ldsw_T0_T1();
                         break;
                     }
+                    gen_movl_reg_T0(s, rd);
                 } else {
                     /* store */
+                    gen_movl_T0_reg(s, rd);
                     gen_op_stw_T0_T1();
                 }
                 if (!(insn & (1 << 24))) {