)]}'
{
  "commit": "e68cc2e5cd28333ac76d757ed2db7d2f7635d09a",
  "tree": "53709591b02fa3c0415847ac1154ebc94fd71fe1",
  "parents": [
    "af1e669cef162e8d9b5f2f176e8b909d61c4b530"
  ],
  "author": {
    "name": "wangyang",
    "email": "wangyang25@otcaix.iscas.ac.cn",
    "time": "Thu Aug 13 18:39:06 2026 +0800"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Mon Aug 24 11:21:08 2026 +1000"
  },
  "message": "target/riscv: enforce even register constraints for Zdinx fcvt pairs\n\nfcvt.d.h and fcvt.h.d access a 64-bit double held in a register\npair, so under Zdinx/Zhinxmin the odd-rd (fcvt.d.h) and odd-rs1\n(fcvt.h.d) encodings are reserved.  Add the missing REQUIRE_EVEN\nchecks so those encodings raise an illegal-instruction exception\ninstead of retiring.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/4109\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nSigned-off-by: wangyang \u003cwangyang25@otcaix.iscas.ac.cn\u003e\nMessage-ID: \u003cea287909fd6043e0bbcdbfdcb0cc8063@wangyang25.otcaix.iscas.ac.cn\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "88711fb07698dc2f556299eb211c08a27d407c37",
      "old_mode": 33188,
      "old_path": "target/riscv/tcg/insn_trans/trans_rvzfh.c.inc",
      "new_id": "b17ef9541c348757f8064d45f6dc85deac3505d4",
      "new_mode": 33188,
      "new_path": "target/riscv/tcg/insn_trans/trans_rvzfh.c.inc"
    }
  ]
}