)]}'
{
  "commit": "e3e477c3bca0beaf9326e0213d52ad4be804fb73",
  "tree": "c89ad02afb43bcd8195b6916e902c35d9962c9a5",
  "parents": [
    "2bb9d628a7e1250db031682b0b59b128e1526da7"
  ],
  "author": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Tue Jul 11 13:06:19 2023 +0200"
  },
  "committer": {
    "name": "Richard Henderson",
    "email": "richard.henderson@linaro.org",
    "time": "Tue Jul 11 15:58:37 2023 +0100"
  },
  "message": "configure: Fix cross-building for RISCV host\n\nWhile when building on native Linux the host architecture\nis reported as \"riscv32\" or \"riscv64\":\n\n  Host machine cpu family: riscv64\n  Host machine cpu: riscv64\n  Found pkg-config: /usr/bin/pkg-config (0.29.2)\n\nSince commit ba0e733362 (\"configure: Merge riscv32 and riscv64\nhost architectures\"), when cross-compiling it is detected as\n\"riscv\". Meson handles the cross-detection but displays a warning:\n\n  WARNING: Unknown CPU family riscv, please report this at https://github.com/mesonbuild/meson/issues/new\n  Host machine cpu family: riscv\n  Host machine cpu: riscv\n  Target machine cpu family: riscv\n  Target machine cpu: riscv\n  Found pkg-config: /usr/bin/riscv64-linux-gnu-pkg-config (1.8.1)\n\nNow since commit 278c1bcef5 (\"target/riscv: Only unify \u0027riscv32/64\u0027\n-\u003e \u0027riscv\u0027 for host cpu in meson\") Meson expects the cpu to be in\n[riscv32, riscv64]. So when cross-building (for example on our\ncross-riscv64-system Gitlab-CI job) we get:\n\n  WARNING: Unknown CPU family riscv, please report this at https://github.com/mesonbuild/meson/issues/new\n  Host machine cpu family: riscv\n  Host machine cpu: riscv\n  Target machine cpu family: riscv\n  Target machine cpu: riscv\n  ../meson.build:684:6: ERROR: Problem encountered: Unsupported CPU riscv, try --enable-tcg-interpreter\n\nFix by partially revert commit ba0e733362 so when cross-building\nthe ./configure script passes the proper host architecture to meson.\n\nFixes: ba0e733362 (\"configure: Merge riscv32 and riscv64 host architectures\")\nFixes: 278c1bcef5 (\"target/riscv: Only unify \u0027riscv32/64\u0027 -\u003e \u0027riscv\u0027 for host cpu in meson\")\nReported-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-Id: \u003c20230711110619.56588-1-philmd@linaro.org\u003e\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2b41c49c0d139c3b9142d62e0898854303897a1a",
      "old_mode": 33261,
      "old_path": "configure",
      "new_id": "dffd44c0595fbc56a46debe57394279fd3bbb2d1",
      "new_mode": 33261,
      "new_path": "configure"
    }
  ]
}