commit e2dca2dc5abfba504d4ac9222673a9edbc1c1266
author Daniel Henrique Barboza <dbarboza@ventanamicro.com> Mon Jan 06 14:37:33 2025 -0300
committer Alistair Francis <alistair.francis@wdc.com> Sun Jan 19 09:44:34 2025 +1000
tree 08570ccbaa1645d0cac6c778bd4ff178a70de32a
parent f4df21e07f126eab24adf505cb33db0c94968cab

target/riscv: use RISCVException enum in exception helpers

Do a cosmetic change in riscv_raise_exception() to change 'exception'
type from uint32_t to RISCVException, making it a bit clear that the
arg is directly correlated to the RISCVException enum.

As a side effect, change 'excp' type from int to RISCVException in
generate_exception() to guarantee that all callers of
riscv_raise_exception() will use the enum.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250106173734.412353-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/cpu.h

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 252fdb8..3d9c404 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -606,7 +606,8 @@
                           int *max_insns, vaddr pc, void *host_pc);
 
 G_NORETURN void riscv_raise_exception(CPURISCVState *env,
-                                      uint32_t exception, uintptr_t pc);
+                                      RISCVException exception,
+                                      uintptr_t pc);
 
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);

target/riscv/op_helper.c

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index eddedac..29c104b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -27,7 +27,8 @@
 
 /* Exceptions processing helpers */
 G_NORETURN void riscv_raise_exception(CPURISCVState *env,
-                                      uint32_t exception, uintptr_t pc)
+                                      RISCVException exception,
+                                      uintptr_t pc)
 {
     CPUState *cs = env_cpu(env);
     cs->exception_index = exception;

target/riscv/translate.c

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a992d4f..f46d76c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -245,7 +245,7 @@
     ctx->pc_save = ctx->base.pc_next + diff;
 }
 
-static void generate_exception(DisasContext *ctx, int excp)
+static void generate_exception(DisasContext *ctx, RISCVException excp)
 {
     gen_update_pc(ctx, 0);
     gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));