)]}'
{
  "commit": "e17801e1708da60371550af5a67e14c7d8db4eae",
  "tree": "8050639d0e2993e52fca34021e3637c283e51fcd",
  "parents": [
    "f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Thu Apr 06 15:03:44 2023 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Fri May 05 10:49:50 2023 +1000"
  },
  "message": "target/riscv: remove cpu-\u003ecfg.ext_u\n\nCreate a new \"u\" RISCVCPUMisaExtConfig property that will update\nenv-\u003emisa_ext* with RVU. Instances of cpu-\u003ecfg.ext_u and similar are\nreplaced with riscv_has_ext(env, RVU).\n\nRemove the old \"u\" property and \u0027ext_u\u0027 from RISCVCPUConfig.\n\nSigned-off-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Weiwei Li \u003cliweiwei@iscas.ac.cn\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-Id: \u003c20230406180351.570807-14-dbarboza@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cded82ac7adeb55e03c361108fff872b4bfaeee9",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.c",
      "new_id": "9565495839f88904fb12aea2355a74648c0c64c5",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.c"
    },
    {
      "type": "modify",
      "old_id": "8b8e541e5f26c6b4c1abff1823cf40f078110d37",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.h",
      "new_id": "486061589ed026c4076dfe835b01c9aa7ddf8d12",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.h"
    }
  ]
}