| commit | dff5f515409f1c9c10df00160524b21381cbef26 | [log] [tgz] |
|---|---|---|
| author | Jim Shu <jim.shu@sifive.com> | Mon May 19 22:35:18 2025 +0800 |
| committer | Alistair Francis <alistair.francis@wdc.com> | Fri Jul 04 21:09:48 2025 +1000 |
| tree | 7a40811901b8551bdf62d7ebdd9812b48a458d90 | |
| parent | 3cb2edae740121cf5da3a9adb8190051e866eb01 [diff] |
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. Signed-off-by: Jim Shu <jim.shu@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250519143518.11086-5-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>