)]}'
{
  "commit": "df6fe2abf2e990f767ce755d426bc439c7bba336",
  "tree": "6752f0c7a1a6cb49e19a6d505b72992f24d2ac1f",
  "parents": [
    "84d1639f286fed00f8a48f417992afc80af48426",
    "083fef73585dfa03f72055ace6de8dec4912d0b0"
  ],
  "author": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Mon Jul 07 09:22:41 2025 -0400"
  },
  "committer": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Mon Jul 07 09:22:41 2025 -0400"
  },
  "message": "Merge tag \u0027pull-target-arm-20250704\u0027 of https://gitlab.com/pm215/qemu into staging\n\ntarget-arm queue:\n * Implement emulation of SME2p1 and SVE2p1\n * Correctly enforce alignment checks for v8M loads and\n   stores done via helper functions\n * Mark the \"highbank\" and the \"midway\" machine as deprecated\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhoABMZHHBldGVyLm1h\n# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3n5CD/9esli7dCvutRUv0YCDR0ca\n# HyFgZT5Z+rnjdUgIBWk3qPIdmQ+dCvK8gci8Du8mY7WWPvJFc+x2wE9b0trxaARZ\n# ckjPo/dPq18FPRqppbNo5LGeBImwVqMYioJtuLIDw6vdMlm6eYvyyJWoFo6pXXPY\n# 3FlW0vBWZ78/KlQ8dYVK8TQryT2qswjXqvhz96/wCFQWRyWCXNosgETGQQH2z/20\n# y5qAMkmI3NATaSSnkVox88RipFSnqotKSpczG5MBXs/n4hZvMHHNfrNxgZ17lygP\n# WI4R5j/M3cRHnglRzxVm5xzz0Vy8gWV+Zn97YMN2syJhze2nFQDcD6dWGNEYdCgT\n# R83/FF2yVn7v4ZompmyL97eUtfiFR/t40M+ojdhrfwADNelAU0JbeLahJuJjXfBm\n# ptdiTnDXYD8Ts6X+FTCafWO9ciPmPJ+SyXOcDnRpy8NpNstL6e7Um5BU8Tcw41nV\n# cAP5K5LooQO6yDkrVf2sjFCU9QxamPhCck+xQsT85njy3br3OA2MTGA/ZdD5noet\n# i2EIcdovQjMZqRv/P8c/+WzDhUw27fPbMzLOvl+nUHQM29Mx7hdTvbdvj/CiQtpV\n# wXprWqdG6jeAXeIkhwFs6/8Uc+7mn3guPi8RQZ5uwX5e1pYNSVOKMjGpooVekNbL\n# qjb+ZLPXIpkCV3N5Vbg9Uw\u003d\u003d\n# \u003donnF\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Fri 04 Jul 2025 12:23:47 EDT\n# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE\n# gpg:                issuer \"peter.maydell@linaro.org\"\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@gmail.com\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@chiark.greenend.org.uk\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpeter@archaic.org.uk\u003e\" [unknown]\n# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE\n\n* tag \u0027pull-target-arm-20250704\u0027 of https://gitlab.com/pm215/qemu: (119 commits)\n  linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1\n  target/arm: Enable FEAT_SME2p1 on -cpu max\n  target/arm: Implement SME2 BFMOPA (non-widening)\n  target/arm: Implement FMOPA (non-widening) for fp16\n  target/arm: Support FPCR.AH in SME FMOPS, BFMOPS\n  target/arm: Rename BFMOPA to BFMOPA_w\n  target/arm: Rename FMOPA_h to FMOPA_w_h\n  target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1\n  target/arm: Implement MOVAZ for SME2p1\n  target/arm: Implement LD1Q, ST1Q for SVE2p1\n  target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1\n  target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h\n  target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1\n  target/arm: Split the ST_zpri and ST_zprr patterns\n  target/arm: Implement SME2 counted predicate register load/store\n  target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1\n  target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1\n  target/arm: Implement PMOV for SME2p1/SVE2p1\n  target/arm: Implement EXTQ for SME2p1/SVE2p1\n  target/arm: Implement DUPQ for SME2p1/SVE2p1\n  ...\n\nSigned-off-by: Stefan Hajnoczi \u003cstefanha@redhat.com\u003e\n",
  "tree_diff": []
}