commit dda860b9c031d6a2768f75e5e622545d41d4b688
author Peter Maydell <peter.maydell@linaro.org> Mon Apr 10 19:46:09 2023 +0100
committer Peter Maydell <peter.maydell@linaro.org> Mon Apr 10 19:46:09 2023 +0100
tree 5784d470ab84fc77934ce4a36594d4ade88fe9a7
parent 26aeb3b5894e0f3d17354e306002c59fa060e1c5
parent 20861f34e0808bd06a0b7d74f8bd29c29e516ca5

Merge tag 'pull-tcg-20230410' of https://gitlab.com/rth7680/qemu into staging

Fix Int128 function call abi for ppc32, mips o32, and _WIN64

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQ0LAIdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8Y8Af9H3h7arUdO0KfFtpr
# UbL4KrTs5JcCJmqgnqAAdkYRCTbdXnGUO9gRFKXWY1+zqMZo7aeA8laE+qh6+6Vy
# WE8OsyPjqkSRJorLZnyX+2iNLlIee2d+KdSlYxQuNVtv/a4XdpV+dlQove2Wd2yy
# 0krswayiYxAfFV52n3Lvqv2kS0kywdhWWdUy11ndRqcYypuw9qdWF1wkpZk1v/Lv
# ZbHe9oiJ610o274ocjpKcSLJFQvaeT/+WDJ3QaqQI8mklcMhampP3kfS27DGK6FH
# O621PxgpVqpVTkOCRXJyMIWCpXabJ4YttMhDQjuAFRghzBvR5Krs2LFmTR7Fkwuo
# F9NUJg==
# =z+vz
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 10 Apr 2023 16:32:18 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230410' of https://gitlab.com/rth7680/qemu:
  tcg/ppc: Fix TCG_TARGET_CALL_{ARG,RET}_I128 for ppc32
  tcg/mips: Fix TCG_TARGET_CALL_RET_I128 for o32 abi
  tcg/i386: Adjust assert in tcg_out_addi_ptr

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/ptw.c

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index ec3f517..6d72950 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1585,11 +1585,6 @@
         result->f.attrs.secure = false;
     }
 
-    /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB.  */
-    if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
-        result->f.guarded = extract64(attrs, 50, 1); /* GP */
-    }
-
     if (regime_is_stage2(mmu_idx)) {
         result->cacheattrs.is_s2_format = true;
         result->cacheattrs.attrs = extract32(attrs, 2, 4);
@@ -1600,6 +1595,11 @@
         assert(attrindx <= 7);
         result->cacheattrs.is_s2_format = false;
         result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
+
+        /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
+        if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
+            result->f.guarded = extract64(attrs, 50, 1); /* GP */
+        }
     }
 
     /*
@@ -2576,6 +2576,7 @@
 
     assert(!s1.is_s2_format);
     ret.is_s2_format = false;
+    ret.guarded = s1.guarded;
 
     if (s1.attrs == 0xf0) {
         tagged = true;