commit db9f1dac4854199b17121eafcb2baf512bd5bf5c
author Hou Weiying <weiying_hou@outlook.com> Mon Apr 19 16:16:38 2021 +1000
committer Alistair Francis <alistair.francis@wdc.com> Tue May 11 20:02:06 2021 +1000
tree 25be15bb82a286822f0b51fb7b1f46463084308f
parent 94c6ba83c1a1e45558bd32421b85233053a1c6f3

target/riscv: Define ePMP mseccfg

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

target/riscv/cpu_bits.h

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8549d77..24d8993 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -220,6 +220,9 @@
 #define CSR_MTINST          0x34a
 #define CSR_MTVAL2          0x34b
 
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG         0x390
+#define CSR_MSECCFGH        0x391
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1