target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 993bf89..d1ffc7b 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -35,7 +35,7 @@
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
- return riscv_cpu_is_32bit(&harts->harts[0].env);
+ return harts->harts[0].env.misa_mxl_max == MXL_RV32;
}
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 01badea..37963be 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -775,7 +775,7 @@
#if defined(TARGET_ARM)
return is_a64(env);
#elif defined(TARGET_RISCV)
- return !riscv_cpu_is_32bit(env);
+ return riscv_cpu_mxl(env) != MXL_RV32;
#else
#error un-handled architecture
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f18bb4b..3d144af 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -108,11 +108,6 @@
}
}
-bool riscv_cpu_is_32bit(CPURISCVState *env)
-{
- return env->misa_mxl == MXL_RV32;
-}
-
static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
{
env->misa_mxl_max = env->misa_mxl = mxl;
@@ -249,7 +244,7 @@
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
(target_ulong)(env->mstatus >> 32));
}
@@ -372,10 +367,16 @@
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
RISCVCPU *cpu = RISCV_CPU(s);
- if (riscv_cpu_is_32bit(&cpu->env)) {
+
+ switch (riscv_cpu_mxl(&cpu->env)) {
+ case MXL_RV32:
info->print_insn = print_insn_riscv32;
- } else {
+ break;
+ case MXL_RV64:
info->print_insn = print_insn_riscv64;
+ break;
+ default:
+ g_assert_not_reached();
}
}
@@ -634,10 +635,13 @@
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- if (riscv_cpu_is_32bit(env)) {
+ switch (riscv_cpu_mxl(env)) {
+ case MXL_RV32:
return g_strdup("riscv:rv32");
- } else {
+ case MXL_RV64:
return g_strdup("riscv:rv64");
+ default:
+ g_assert_not_reached();
}
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 90d11e3..e23157b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -396,7 +396,14 @@
FIELD(TB_FLAGS, HLSX, 10, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
-bool riscv_cpu_is_32bit(CPURISCVState *env);
+#ifdef TARGET_RISCV32
+#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+{
+ return env->misa_mxl;
+}
+#endif
/*
* A simplification for VLMAX
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 14d1d3c..403f541 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -152,7 +152,7 @@
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
- uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
+ uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
MSTATUS64_UXL | sd;
@@ -447,7 +447,7 @@
if (first_stage == true) {
if (use_background) {
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->vsatp, SATP32_MODE);
} else {
@@ -455,7 +455,7 @@
vm = get_field(env->vsatp, SATP64_MODE);
}
} else {
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP32_MODE);
} else {
@@ -465,7 +465,7 @@
}
widened = 0;
} else {
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP32_MODE);
} else {
@@ -558,7 +558,7 @@
}
target_ulong pte;
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
} else {
pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
@@ -678,7 +678,7 @@
int page_fault_exceptions, vm;
uint64_t stap_mode;
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
stap_mode = SATP32_MODE;
} else {
stap_mode = SATP64_MODE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d0c86a3..9c0753b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -95,7 +95,7 @@
}
break;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
switch (csrno) {
case CSR_CYCLEH:
if (!get_field(env->hcounteren, COUNTEREN_CY) &&
@@ -130,7 +130,7 @@
static RISCVException ctr32(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -145,7 +145,7 @@
static RISCVException any32(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -180,7 +180,7 @@
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
if (riscv_cpu_virt_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
@@ -486,7 +486,7 @@
static int validate_vm(CPURISCVState *env, target_ulong vm)
{
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
return valid_vm_1_10_32[vm & 0xf];
} else {
return valid_vm_1_10_64[vm & 0xf];
@@ -510,7 +510,7 @@
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW;
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
@@ -522,7 +522,7 @@
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
} else {
mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
@@ -795,7 +795,7 @@
{
target_ulong mask = (sstatus_v1_10_mask);
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
mask |= SSTATUS32_SD;
} else {
mask |= SSTATUS64_SD;
@@ -1006,7 +1006,7 @@
return RISCV_EXCP_NONE;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
vm = validate_vm(env, get_field(val, SATP32_MODE));
mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
asid = (val ^ env->satp) & SATP32_ASID;
@@ -1034,7 +1034,7 @@
target_ulong *val)
{
*val = env->hstatus;
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
}
@@ -1047,7 +1047,7 @@
target_ulong val)
{
env->hstatus = val;
- if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
+ if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
}
if (get_field(val, HSTATUS_VSBE) != 0) {
@@ -1215,7 +1215,7 @@
return RISCV_EXCP_ILLEGAL_INST;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
} else {
env->htimedelta = val;
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 5257df0..2342917 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -161,7 +161,7 @@
CPURISCVState *env = &cpu->env;
GString *s = g_string_new(NULL);
riscv_csr_predicate_fn predicate;
- int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
+ int bitsize = 16 << env->misa_mxl_max;
int i;
g_string_printf(s, "<?xml version=\"1.0\"?>");
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index f7e6ea7..7efb4b6 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -150,7 +150,7 @@
target_ulong last_size;
int last_attr;
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP32_MODE);
} else {
@@ -220,7 +220,7 @@
return;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
if (!(env->satp & SATP32_MODE)) {
monitor_printf(mon, "No translation or protection\n");
return;
