commit daf9748ac002ec35258e5986b6257961fd04b565
author Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Sun May 26 13:45:51 2024 -0700
committer Peter Maydell <peter.maydell@linaro.org> Thu May 30 15:45:21 2024 +0100
tree 49d0de848dd4ce7a9678af8bfad831e722df9269
parent fa31b7e1681cfe20917f172b537a3a0988efc583

target/arm: Disable SVE extensions when SVE is disabled

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304
Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20240526204551.553282-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/cpu64.c

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c15d086..862d2b9 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -109,7 +109,11 @@
          * No explicit bits enabled, and no implicit bits from sve-max-vq.
          */
         if (!cpu_isar_feature(aa64_sve, cpu)) {
-            /* SVE is disabled and so are all vector lengths.  Good. */
+            /*
+             * SVE is disabled and so are all vector lengths.  Good.
+             * Disable all SVE extensions as well.
+             */
+            cpu->isar.id_aa64zfr0 = 0;
             return;
         }