)]}'
{
  "commit": "daafa78b297291fea36fb4daeed526705fa7c035",
  "tree": "f5882bfdea9d8fc0ed7228e3a3711a14f420e06f",
  "parents": [
    "cd2a2788a92c39aa6405e2ff7a95aca02d036757"
  ],
  "author": {
    "name": "Andrey Shumilin",
    "email": "shum.sdl@nppct.ru",
    "time": "Thu May 23 16:06:20 2024 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue May 28 14:20:48 2024 +0100"
  },
  "message": "hw/intc/arm_gic: Fix handling of NS view of GICC_APR\u003cn\u003e\n\nIn gic_cpu_read() and gic_cpu_write(), we delegate the handling of\nreading and writing the Non-Secure view of the GICC_APR\u003cn\u003e registers\nto functions gic_apr_ns_view() and gic_apr_write_ns_view().\nUnfortunately we got the order of the arguments wrong, swapping the\nCPU number and the register number (which the compiler doesn\u0027t catch\nbecause they\u0027re both integers).\n\nMost guests probably didn\u0027t notice this bug because directly\naccessing the APR registers is typically something only done by\nfirmware when it is doing state save for going into a sleep mode.\n\nCorrect the mismatched call arguments.\n\nFound by Linux Verification Center (linuxtesting.org) with SVACE.\n\nCc: qemu-stable@nongnu.org\nFixes: 51fd06e0ee (\"hw/intc/arm_gic: Fix handling of GICC_APR\u003cn\u003e, GICC_NSAPR\u003cn\u003e registers\")\nSigned-off-by: Andrey Shumilin \u003cshum.sdl@nppct.ru\u003e\n[PMM: Rewrote commit message]\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Alex Bennée\u003calex.bennee@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "074cf50af25da0321eecf1e42c0d4d9fc86e2a04",
      "old_mode": 33188,
      "old_path": "hw/intc/arm_gic.c",
      "new_id": "e4b8437f8b8e9063630fd4dc7d25df041d1033e7",
      "new_mode": 33188,
      "new_path": "hw/intc/arm_gic.c"
    }
  ]
}