diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index b28ee93..b4c98fc 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -67,25 +67,25 @@
 }
 #endif
 
-target_ulong helper_clo (target_ulong t0)
+target_ulong helper_clo (target_ulong arg1)
 {
-    return clo32(t0);
+    return clo32(arg1);
 }
 
-target_ulong helper_clz (target_ulong t0)
+target_ulong helper_clz (target_ulong arg1)
 {
-    return clz32(t0);
+    return clz32(arg1);
 }
 
 #if defined(TARGET_MIPS64)
-target_ulong helper_dclo (target_ulong t0)
+target_ulong helper_dclo (target_ulong arg1)
 {
-    return clo64(t0);
+    return clo64(arg1);
 }
 
-target_ulong helper_dclz (target_ulong t0)
+target_ulong helper_dclz (target_ulong arg1)
 {
-    return clz64(t0);
+    return clz64(arg1);
 }
 #endif /* TARGET_MIPS64 */
 
@@ -101,126 +101,126 @@
     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 }
 
-static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
+static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
 {
     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
-    t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
+    arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 }
 
-static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
+static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
 {
-    t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
+    arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 }
 
 /* Multiplication variants of the vr54xx. */
-target_ulong helper_muls (target_ulong t0, target_ulong t1)
+target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_mulsu (target_ulong t0, target_ulong t1)
+target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_macc (target_ulong t0, target_ulong t1)
+target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_macchi (target_ulong t0, target_ulong t1)
+target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_maccu (target_ulong t0, target_ulong t1)
+target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_macchiu (target_ulong t0, target_ulong t1)
+target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_msac (target_ulong t0, target_ulong t1)
+target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_msachi (target_ulong t0, target_ulong t1)
+target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_msacu (target_ulong t0, target_ulong t1)
+target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
 {
-    set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_msachiu (target_ulong t0, target_ulong t1)
+target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_mulhi (target_ulong t0, target_ulong t1)
+target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
+    set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)
+target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
+    set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_mulshi (target_ulong t0, target_ulong t1)
+target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+    set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)
+target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
 {
-    set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+    set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
 
-    return t0;
+    return arg1;
 }
 
 #ifdef TARGET_MIPS64
-void helper_dmult (target_ulong t0, target_ulong t1)
+void helper_dmult (target_ulong arg1, target_ulong arg2)
 {
-    muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
+    muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 }
 
-void helper_dmultu (target_ulong t0, target_ulong t1)
+void helper_dmultu (target_ulong arg1, target_ulong arg2)
 {
-    mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
+    mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 }
 #endif
 
@@ -232,7 +232,7 @@
 #define GET_OFFSET(addr, offset) (addr - (offset))
 #endif
 
-target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     target_ulong tmp;
 
@@ -249,27 +249,27 @@
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 
-    if (GET_LMASK(t0) <= 2) {
-        tmp = ldfun(GET_OFFSET(t0, 1));
-        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
+    if (GET_LMASK(arg2) <= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, 1));
+        arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
     }
 
-    if (GET_LMASK(t0) <= 1) {
-        tmp = ldfun(GET_OFFSET(t0, 2));
-        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
+    if (GET_LMASK(arg2) <= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, 2));
+        arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
     }
 
-    if (GET_LMASK(t0) == 0) {
-        tmp = ldfun(GET_OFFSET(t0, 3));
-        t1 = (t1 & 0xFFFFFF00) | tmp;
+    if (GET_LMASK(arg2) == 0) {
+        tmp = ldfun(GET_OFFSET(arg2, 3));
+        arg1 = (arg1 & 0xFFFFFF00) | tmp;
     }
-    return (int32_t)t1;
+    return (int32_t)arg1;
 }
 
-target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     target_ulong tmp;
 
@@ -286,27 +286,27 @@
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0xFFFFFF00) | tmp;
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0xFFFFFF00) | tmp;
 
-    if (GET_LMASK(t0) >= 1) {
-        tmp = ldfun(GET_OFFSET(t0, -1));
-        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
+    if (GET_LMASK(arg2) >= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, -1));
+        arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
     }
 
-    if (GET_LMASK(t0) >= 2) {
-        tmp = ldfun(GET_OFFSET(t0, -2));
-        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
+    if (GET_LMASK(arg2) >= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, -2));
+        arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
     }
 
-    if (GET_LMASK(t0) == 3) {
-        tmp = ldfun(GET_OFFSET(t0, -3));
-        t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
+    if (GET_LMASK(arg2) == 3) {
+        tmp = ldfun(GET_OFFSET(arg2, -3));
+        arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
     }
-    return (int32_t)t1;
+    return (int32_t)arg1;
 }
 
-void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -321,19 +321,19 @@
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)(t1 >> 24));
+    stfun(arg2, (uint8_t)(arg1 >> 24));
 
-    if (GET_LMASK(t0) <= 2)
-        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
+    if (GET_LMASK(arg2) <= 2)
+        stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK(t0) <= 1)
-        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
+    if (GET_LMASK(arg2) <= 1)
+        stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK(t0) == 0)
-        stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
+    if (GET_LMASK(arg2) == 0)
+        stfun(GET_OFFSET(arg2, 3), (uint8_t)arg1);
 }
 
-void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -348,16 +348,16 @@
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)t1);
+    stfun(arg2, (uint8_t)arg1);
 
-    if (GET_LMASK(t0) >= 1)
-        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
+    if (GET_LMASK(arg2) >= 1)
+        stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK(t0) >= 2)
-        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
+    if (GET_LMASK(arg2) >= 2)
+        stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK(t0) == 3)
-        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
+    if (GET_LMASK(arg2) == 3)
+        stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
 }
 
 #if defined(TARGET_MIPS64)
@@ -370,7 +370,7 @@
 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 #endif
 
-target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     uint64_t tmp;
 
@@ -387,48 +387,48 @@
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 
-    if (GET_LMASK64(t0) <= 6) {
-        tmp = ldfun(GET_OFFSET(t0, 1));
-        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
+    if (GET_LMASK64(arg2) <= 6) {
+        tmp = ldfun(GET_OFFSET(arg2, 1));
+        arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
     }
 
-    if (GET_LMASK64(t0) <= 5) {
-        tmp = ldfun(GET_OFFSET(t0, 2));
-        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
+    if (GET_LMASK64(arg2) <= 5) {
+        tmp = ldfun(GET_OFFSET(arg2, 2));
+        arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
     }
 
-    if (GET_LMASK64(t0) <= 4) {
-        tmp = ldfun(GET_OFFSET(t0, 3));
-        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
+    if (GET_LMASK64(arg2) <= 4) {
+        tmp = ldfun(GET_OFFSET(arg2, 3));
+        arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
     }
 
-    if (GET_LMASK64(t0) <= 3) {
-        tmp = ldfun(GET_OFFSET(t0, 4));
-        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
+    if (GET_LMASK64(arg2) <= 3) {
+        tmp = ldfun(GET_OFFSET(arg2, 4));
+        arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
     }
 
-    if (GET_LMASK64(t0) <= 2) {
-        tmp = ldfun(GET_OFFSET(t0, 5));
-        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
+    if (GET_LMASK64(arg2) <= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, 5));
+        arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
     }
 
-    if (GET_LMASK64(t0) <= 1) {
-        tmp = ldfun(GET_OFFSET(t0, 6));
-        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
+    if (GET_LMASK64(arg2) <= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, 6));
+        arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
     }
 
-    if (GET_LMASK64(t0) == 0) {
-        tmp = ldfun(GET_OFFSET(t0, 7));
-        t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
+    if (GET_LMASK64(arg2) == 0) {
+        tmp = ldfun(GET_OFFSET(arg2, 7));
+        arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
     }
 
-    return t1;
+    return arg1;
 }
 
-target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
+target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
     uint64_t tmp;
 
@@ -445,48 +445,48 @@
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(t0);
-    t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
+    tmp = ldfun(arg2);
+    arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 
-    if (GET_LMASK64(t0) >= 1) {
-        tmp = ldfun(GET_OFFSET(t0, -1));
-        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
+    if (GET_LMASK64(arg2) >= 1) {
+        tmp = ldfun(GET_OFFSET(arg2, -1));
+        arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
     }
 
-    if (GET_LMASK64(t0) >= 2) {
-        tmp = ldfun(GET_OFFSET(t0, -2));
-        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
+    if (GET_LMASK64(arg2) >= 2) {
+        tmp = ldfun(GET_OFFSET(arg2, -2));
+        arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
     }
 
-    if (GET_LMASK64(t0) >= 3) {
-        tmp = ldfun(GET_OFFSET(t0, -3));
-        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
+    if (GET_LMASK64(arg2) >= 3) {
+        tmp = ldfun(GET_OFFSET(arg2, -3));
+        arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
     }
 
-    if (GET_LMASK64(t0) >= 4) {
-        tmp = ldfun(GET_OFFSET(t0, -4));
-        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
+    if (GET_LMASK64(arg2) >= 4) {
+        tmp = ldfun(GET_OFFSET(arg2, -4));
+        arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
     }
 
-    if (GET_LMASK64(t0) >= 5) {
-        tmp = ldfun(GET_OFFSET(t0, -5));
-        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
+    if (GET_LMASK64(arg2) >= 5) {
+        tmp = ldfun(GET_OFFSET(arg2, -5));
+        arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
     }
 
-    if (GET_LMASK64(t0) >= 6) {
-        tmp = ldfun(GET_OFFSET(t0, -6));
-        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
+    if (GET_LMASK64(arg2) >= 6) {
+        tmp = ldfun(GET_OFFSET(arg2, -6));
+        arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
     }
 
-    if (GET_LMASK64(t0) == 7) {
-        tmp = ldfun(GET_OFFSET(t0, -7));
-        t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
+    if (GET_LMASK64(arg2) == 7) {
+        tmp = ldfun(GET_OFFSET(arg2, -7));
+        arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
     }
 
-    return t1;
+    return arg1;
 }
 
-void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -501,31 +501,31 @@
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)(t1 >> 56));
+    stfun(arg2, (uint8_t)(arg1 >> 56));
 
-    if (GET_LMASK64(t0) <= 6)
-        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
+    if (GET_LMASK64(arg2) <= 6)
+        stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48));
 
-    if (GET_LMASK64(t0) <= 5)
-        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
+    if (GET_LMASK64(arg2) <= 5)
+        stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40));
 
-    if (GET_LMASK64(t0) <= 4)
-        stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
+    if (GET_LMASK64(arg2) <= 4)
+        stfun(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32));
 
-    if (GET_LMASK64(t0) <= 3)
-        stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
+    if (GET_LMASK64(arg2) <= 3)
+        stfun(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24));
 
-    if (GET_LMASK64(t0) <= 2)
-        stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
+    if (GET_LMASK64(arg2) <= 2)
+        stfun(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK64(t0) <= 1)
-        stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
+    if (GET_LMASK64(arg2) <= 1)
+        stfun(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK64(t0) <= 0)
-        stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
+    if (GET_LMASK64(arg2) <= 0)
+        stfun(GET_OFFSET(arg2, 7), (uint8_t)arg1);
 }
 
-void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
+void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -540,28 +540,28 @@
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(t0, (uint8_t)t1);
+    stfun(arg2, (uint8_t)arg1);
 
-    if (GET_LMASK64(t0) >= 1)
-        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
+    if (GET_LMASK64(arg2) >= 1)
+        stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
 
-    if (GET_LMASK64(t0) >= 2)
-        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
+    if (GET_LMASK64(arg2) >= 2)
+        stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
 
-    if (GET_LMASK64(t0) >= 3)
-        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
+    if (GET_LMASK64(arg2) >= 3)
+        stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
 
-    if (GET_LMASK64(t0) >= 4)
-        stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
+    if (GET_LMASK64(arg2) >= 4)
+        stfun(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32));
 
-    if (GET_LMASK64(t0) >= 5)
-        stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
+    if (GET_LMASK64(arg2) >= 5)
+        stfun(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40));
 
-    if (GET_LMASK64(t0) >= 6)
-        stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
+    if (GET_LMASK64(arg2) >= 6)
+        stfun(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48));
 
-    if (GET_LMASK64(t0) == 7)
-        stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
+    if (GET_LMASK64(arg2) == 7)
+        stfun(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56));
 }
 #endif /* TARGET_MIPS64 */
 
@@ -805,7 +805,7 @@
 }
 #endif /* TARGET_MIPS64 */
 
-void helper_mtc0_index (target_ulong t0)
+void helper_mtc0_index (target_ulong arg1)
 {
     int num = 1;
     unsigned int tmp = env->tlb->nb_tlb;
@@ -814,10 +814,10 @@
         tmp >>= 1;
         num <<= 1;
     } while (tmp);
-    env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
+    env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 }
 
-void helper_mtc0_mvpcontrol (target_ulong t0)
+void helper_mtc0_mvpcontrol (target_ulong arg1)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -827,21 +827,21 @@
                 (1 << CP0MVPCo_EVP);
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0MVPCo_STLB);
-    newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
+    newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 
     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 
     env->mvp->CP0_MVPControl = newval;
 }
 
-void helper_mtc0_vpecontrol (target_ulong t0)
+void helper_mtc0_vpecontrol (target_ulong arg1)
 {
     uint32_t mask;
     uint32_t newval;
 
     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
-    newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
+    newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 
     /* Yield scheduler intercept not implemented. */
     /* Gating storage scheduler intercept not implemented. */
@@ -851,7 +851,7 @@
     env->CP0_VPEControl = newval;
 }
 
-void helper_mtc0_vpeconf0 (target_ulong t0)
+void helper_mtc0_vpeconf0 (target_ulong arg1)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -861,14 +861,14 @@
             mask |= (0xff << CP0VPEC0_XTC);
         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
     }
-    newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
+    newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
 
     // TODO: TC exclusive handling due to ERL/EXL.
 
     env->CP0_VPEConf0 = newval;
 }
 
-void helper_mtc0_vpeconf1 (target_ulong t0)
+void helper_mtc0_vpeconf1 (target_ulong arg1)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -876,7 +876,7 @@
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                 (0xff << CP0VPEC1_NCP1);
-    newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
+    newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
 
     /* UDI not implemented. */
     /* CP2 not implemented. */
@@ -886,60 +886,60 @@
     env->CP0_VPEConf1 = newval;
 }
 
-void helper_mtc0_yqmask (target_ulong t0)
+void helper_mtc0_yqmask (target_ulong arg1)
 {
     /* Yield qualifier inputs not implemented. */
     env->CP0_YQMask = 0x00000000;
 }
 
-void helper_mtc0_vpeopt (target_ulong t0)
+void helper_mtc0_vpeopt (target_ulong arg1)
 {
-    env->CP0_VPEOpt = t0 & 0x0000ffff;
+    env->CP0_VPEOpt = arg1 & 0x0000ffff;
 }
 
-void helper_mtc0_entrylo0 (target_ulong t0)
+void helper_mtc0_entrylo0 (target_ulong arg1)
 {
     /* Large physaddr (PABITS) not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
+    env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
 }
 
-void helper_mtc0_tcstatus (target_ulong t0)
+void helper_mtc0_tcstatus (target_ulong arg1)
 {
     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
     uint32_t newval;
 
-    newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask);
+    newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
 
     // TODO: Sync with CP0_Status.
 
     env->active_tc.CP0_TCStatus = newval;
 }
 
-void helper_mttc0_tcstatus (target_ulong t0)
+void helper_mttc0_tcstatus (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     // TODO: Sync with CP0_Status.
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCStatus = t0;
+        env->active_tc.CP0_TCStatus = arg1;
     else
-        env->tcs[other_tc].CP0_TCStatus = t0;
+        env->tcs[other_tc].CP0_TCStatus = arg1;
 }
 
-void helper_mtc0_tcbind (target_ulong t0)
+void helper_mtc0_tcbind (target_ulong arg1)
 {
     uint32_t mask = (1 << CP0TCBd_TBE);
     uint32_t newval;
 
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0TCBd_CurVPE);
-    newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
+    newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
     env->active_tc.CP0_TCBind = newval;
 }
 
-void helper_mttc0_tcbind (target_ulong t0)
+void helper_mttc0_tcbind (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     uint32_t mask = (1 << CP0TCBd_TBE);
@@ -948,122 +948,122 @@
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0TCBd_CurVPE);
     if (other_tc == env->current_tc) {
-        newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
+        newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
         env->active_tc.CP0_TCBind = newval;
     } else {
-        newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask);
+        newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
         env->tcs[other_tc].CP0_TCBind = newval;
     }
 }
 
-void helper_mtc0_tcrestart (target_ulong t0)
+void helper_mtc0_tcrestart (target_ulong arg1)
 {
-    env->active_tc.PC = t0;
+    env->active_tc.PC = arg1;
     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
     env->CP0_LLAddr = 0ULL;
     /* MIPS16 not implemented. */
 }
 
-void helper_mttc0_tcrestart (target_ulong t0)
+void helper_mttc0_tcrestart (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc) {
-        env->active_tc.PC = t0;
+        env->active_tc.PC = arg1;
         env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
         env->CP0_LLAddr = 0ULL;
         /* MIPS16 not implemented. */
     } else {
-        env->tcs[other_tc].PC = t0;
+        env->tcs[other_tc].PC = arg1;
         env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
         env->CP0_LLAddr = 0ULL;
         /* MIPS16 not implemented. */
     }
 }
 
-void helper_mtc0_tchalt (target_ulong t0)
+void helper_mtc0_tchalt (target_ulong arg1)
 {
-    env->active_tc.CP0_TCHalt = t0 & 0x1;
+    env->active_tc.CP0_TCHalt = arg1 & 0x1;
 
     // TODO: Halt TC / Restart (if allocated+active) TC.
 }
 
-void helper_mttc0_tchalt (target_ulong t0)
+void helper_mttc0_tchalt (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     // TODO: Halt TC / Restart (if allocated+active) TC.
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCHalt = t0;
+        env->active_tc.CP0_TCHalt = arg1;
     else
-        env->tcs[other_tc].CP0_TCHalt = t0;
+        env->tcs[other_tc].CP0_TCHalt = arg1;
 }
 
-void helper_mtc0_tccontext (target_ulong t0)
+void helper_mtc0_tccontext (target_ulong arg1)
 {
-    env->active_tc.CP0_TCContext = t0;
+    env->active_tc.CP0_TCContext = arg1;
 }
 
-void helper_mttc0_tccontext (target_ulong t0)
+void helper_mttc0_tccontext (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCContext = t0;
+        env->active_tc.CP0_TCContext = arg1;
     else
-        env->tcs[other_tc].CP0_TCContext = t0;
+        env->tcs[other_tc].CP0_TCContext = arg1;
 }
 
-void helper_mtc0_tcschedule (target_ulong t0)
+void helper_mtc0_tcschedule (target_ulong arg1)
 {
-    env->active_tc.CP0_TCSchedule = t0;
+    env->active_tc.CP0_TCSchedule = arg1;
 }
 
-void helper_mttc0_tcschedule (target_ulong t0)
+void helper_mttc0_tcschedule (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCSchedule = t0;
+        env->active_tc.CP0_TCSchedule = arg1;
     else
-        env->tcs[other_tc].CP0_TCSchedule = t0;
+        env->tcs[other_tc].CP0_TCSchedule = arg1;
 }
 
-void helper_mtc0_tcschefback (target_ulong t0)
+void helper_mtc0_tcschefback (target_ulong arg1)
 {
-    env->active_tc.CP0_TCScheFBack = t0;
+    env->active_tc.CP0_TCScheFBack = arg1;
 }
 
-void helper_mttc0_tcschefback (target_ulong t0)
+void helper_mttc0_tcschefback (target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.CP0_TCScheFBack = t0;
+        env->active_tc.CP0_TCScheFBack = arg1;
     else
-        env->tcs[other_tc].CP0_TCScheFBack = t0;
+        env->tcs[other_tc].CP0_TCScheFBack = arg1;
 }
 
-void helper_mtc0_entrylo1 (target_ulong t0)
+void helper_mtc0_entrylo1 (target_ulong arg1)
 {
     /* Large physaddr (PABITS) not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
+    env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
 }
 
-void helper_mtc0_context (target_ulong t0)
+void helper_mtc0_context (target_ulong arg1)
 {
-    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
+    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
 }
 
-void helper_mtc0_pagemask (target_ulong t0)
+void helper_mtc0_pagemask (target_ulong arg1)
 {
     /* 1k pages not implemented */
-    env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
+    env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
 }
 
-void helper_mtc0_pagegrain (target_ulong t0)
+void helper_mtc0_pagegrain (target_ulong arg1)
 {
     /* SmartMIPS not implemented */
     /* Large physaddr (PABITS) not implemented */
@@ -1071,52 +1071,52 @@
     env->CP0_PageGrain = 0;
 }
 
-void helper_mtc0_wired (target_ulong t0)
+void helper_mtc0_wired (target_ulong arg1)
 {
-    env->CP0_Wired = t0 % env->tlb->nb_tlb;
+    env->CP0_Wired = arg1 % env->tlb->nb_tlb;
 }
 
-void helper_mtc0_srsconf0 (target_ulong t0)
+void helper_mtc0_srsconf0 (target_ulong arg1)
 {
-    env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
+    env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
 }
 
-void helper_mtc0_srsconf1 (target_ulong t0)
+void helper_mtc0_srsconf1 (target_ulong arg1)
 {
-    env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
+    env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
 }
 
-void helper_mtc0_srsconf2 (target_ulong t0)
+void helper_mtc0_srsconf2 (target_ulong arg1)
 {
-    env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
+    env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
 }
 
-void helper_mtc0_srsconf3 (target_ulong t0)
+void helper_mtc0_srsconf3 (target_ulong arg1)
 {
-    env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
+    env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
 }
 
-void helper_mtc0_srsconf4 (target_ulong t0)
+void helper_mtc0_srsconf4 (target_ulong arg1)
 {
-    env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
+    env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
 }
 
-void helper_mtc0_hwrena (target_ulong t0)
+void helper_mtc0_hwrena (target_ulong arg1)
 {
-    env->CP0_HWREna = t0 & 0x0000000F;
+    env->CP0_HWREna = arg1 & 0x0000000F;
 }
 
-void helper_mtc0_count (target_ulong t0)
+void helper_mtc0_count (target_ulong arg1)
 {
-    cpu_mips_store_count(env, t0);
+    cpu_mips_store_count(env, arg1);
 }
 
-void helper_mtc0_entryhi (target_ulong t0)
+void helper_mtc0_entryhi (target_ulong arg1)
 {
     target_ulong old, val;
 
     /* 1k pages not implemented */
-    val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
+    val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
 #if defined(TARGET_MIPS64)
     val &= env->SEGMask;
 #endif
@@ -1131,32 +1131,32 @@
         cpu_mips_tlb_flush(env, 1);
 }
 
-void helper_mttc0_entryhi(target_ulong t0)
+void helper_mttc0_entryhi(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     int32_t tcstatus;
 
-    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
+    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
     if (other_tc == env->current_tc) {
-        tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff);
+        tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
         env->active_tc.CP0_TCStatus = tcstatus;
     } else {
-        tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff);
+        tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
         env->tcs[other_tc].CP0_TCStatus = tcstatus;
     }
 }
 
-void helper_mtc0_compare (target_ulong t0)
+void helper_mtc0_compare (target_ulong arg1)
 {
-    cpu_mips_store_compare(env, t0);
+    cpu_mips_store_compare(env, arg1);
 }
 
-void helper_mtc0_status (target_ulong t0)
+void helper_mtc0_status (target_ulong arg1)
 {
     uint32_t val, old;
     uint32_t mask = env->CP0_Status_rw_bitmask;
 
-    val = t0 & mask;
+    val = arg1 & mask;
     old = env->CP0_Status;
     env->CP0_Status = (env->CP0_Status & ~mask) | val;
     compute_hflags(env);
@@ -1175,34 +1175,34 @@
     cpu_mips_update_irq(env);
 }
 
-void helper_mttc0_status(target_ulong t0)
+void helper_mttc0_status(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
 
-    env->CP0_Status = t0 & ~0xf1000018;
-    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
-    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
-    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
+    env->CP0_Status = arg1 & ~0xf1000018;
+    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
+    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
+    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
     if (other_tc == env->current_tc)
         env->active_tc.CP0_TCStatus = tcstatus;
     else
         env->tcs[other_tc].CP0_TCStatus = tcstatus;
 }
 
-void helper_mtc0_intctl (target_ulong t0)
+void helper_mtc0_intctl (target_ulong arg1)
 {
     /* vectored interrupts not implemented, no performance counters. */
-    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
+    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
 }
 
-void helper_mtc0_srsctl (target_ulong t0)
+void helper_mtc0_srsctl (target_ulong arg1)
 {
     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
-    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
+    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
 }
 
-void helper_mtc0_cause (target_ulong t0)
+void helper_mtc0_cause (target_ulong arg1)
 {
     uint32_t mask = 0x00C00300;
     uint32_t old = env->CP0_Cause;
@@ -1210,7 +1210,7 @@
     if (env->insn_flags & ISA_MIPS32R2)
         mask |= 1 << CP0Ca_DC;
 
-    env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
+    env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
 
     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
         if (env->CP0_Cause & (1 << CP0Ca_DC))
@@ -1221,66 +1221,66 @@
 
     /* Handle the software interrupt as an hardware one, as they
        are very similar */
-    if (t0 & CP0Ca_IP_mask) {
+    if (arg1 & CP0Ca_IP_mask) {
         cpu_mips_update_irq(env);
     }
 }
 
-void helper_mtc0_ebase (target_ulong t0)
+void helper_mtc0_ebase (target_ulong arg1)
 {
     /* vectored interrupts not implemented */
     /* Multi-CPU not implemented */
-    env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
+    env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
 }
 
-void helper_mtc0_config0 (target_ulong t0)
+void helper_mtc0_config0 (target_ulong arg1)
 {
-    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
+    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
 }
 
-void helper_mtc0_config2 (target_ulong t0)
+void helper_mtc0_config2 (target_ulong arg1)
 {
     /* tertiary/secondary caches not implemented */
     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
 }
 
-void helper_mtc0_watchlo (target_ulong t0, uint32_t sel)
+void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
 {
     /* Watch exceptions for instructions, data loads, data stores
        not implemented. */
-    env->CP0_WatchLo[sel] = (t0 & ~0x7);
+    env->CP0_WatchLo[sel] = (arg1 & ~0x7);
 }
 
-void helper_mtc0_watchhi (target_ulong t0, uint32_t sel)
+void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
 {
-    env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
-    env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
+    env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
+    env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
 }
 
-void helper_mtc0_xcontext (target_ulong t0)
+void helper_mtc0_xcontext (target_ulong arg1)
 {
     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
-    env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
+    env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
 }
 
-void helper_mtc0_framemask (target_ulong t0)
+void helper_mtc0_framemask (target_ulong arg1)
 {
-    env->CP0_Framemask = t0; /* XXX */
+    env->CP0_Framemask = arg1; /* XXX */
 }
 
-void helper_mtc0_debug (target_ulong t0)
+void helper_mtc0_debug (target_ulong arg1)
 {
-    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
-    if (t0 & (1 << CP0DB_DM))
+    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
+    if (arg1 & (1 << CP0DB_DM))
         env->hflags |= MIPS_HFLAG_DM;
     else
         env->hflags &= ~MIPS_HFLAG_DM;
 }
 
-void helper_mttc0_debug(target_ulong t0)
+void helper_mttc0_debug(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
-    uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
+    uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
 
     /* XXX: Might be wrong, check with EJTAG spec. */
     if (other_tc == env->current_tc)
@@ -1288,32 +1288,32 @@
     else
         env->tcs[other_tc].CP0_Debug_tcstatus = val;
     env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
-                     (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
+                     (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 }
 
-void helper_mtc0_performance0 (target_ulong t0)
+void helper_mtc0_performance0 (target_ulong arg1)
 {
-    env->CP0_Performance0 = t0 & 0x000007ff;
+    env->CP0_Performance0 = arg1 & 0x000007ff;
 }
 
-void helper_mtc0_taglo (target_ulong t0)
+void helper_mtc0_taglo (target_ulong arg1)
 {
-    env->CP0_TagLo = t0 & 0xFFFFFCF6;
+    env->CP0_TagLo = arg1 & 0xFFFFFCF6;
 }
 
-void helper_mtc0_datalo (target_ulong t0)
+void helper_mtc0_datalo (target_ulong arg1)
 {
-    env->CP0_DataLo = t0; /* XXX */
+    env->CP0_DataLo = arg1; /* XXX */
 }
 
-void helper_mtc0_taghi (target_ulong t0)
+void helper_mtc0_taghi (target_ulong arg1)
 {
-    env->CP0_TagHi = t0; /* XXX */
+    env->CP0_TagHi = arg1; /* XXX */
 }
 
-void helper_mtc0_datahi (target_ulong t0)
+void helper_mtc0_datahi (target_ulong arg1)
 {
-    env->CP0_DataHi = t0; /* XXX */
+    env->CP0_DataHi = arg1; /* XXX */
 }
 
 /* MIPS MT functions */
@@ -1367,106 +1367,106 @@
         return env->tcs[other_tc].DSPControl;
 }
 
-void helper_mttgpr(target_ulong t0, uint32_t sel)
+void helper_mttgpr(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.gpr[sel] = t0;
+        env->active_tc.gpr[sel] = arg1;
     else
-        env->tcs[other_tc].gpr[sel] = t0;
+        env->tcs[other_tc].gpr[sel] = arg1;
 }
 
-void helper_mttlo(target_ulong t0, uint32_t sel)
+void helper_mttlo(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.LO[sel] = t0;
+        env->active_tc.LO[sel] = arg1;
     else
-        env->tcs[other_tc].LO[sel] = t0;
+        env->tcs[other_tc].LO[sel] = arg1;
 }
 
-void helper_mtthi(target_ulong t0, uint32_t sel)
+void helper_mtthi(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.HI[sel] = t0;
+        env->active_tc.HI[sel] = arg1;
     else
-        env->tcs[other_tc].HI[sel] = t0;
+        env->tcs[other_tc].HI[sel] = arg1;
 }
 
-void helper_mttacx(target_ulong t0, uint32_t sel)
+void helper_mttacx(target_ulong arg1, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.ACX[sel] = t0;
+        env->active_tc.ACX[sel] = arg1;
     else
-        env->tcs[other_tc].ACX[sel] = t0;
+        env->tcs[other_tc].ACX[sel] = arg1;
 }
 
-void helper_mttdsp(target_ulong t0)
+void helper_mttdsp(target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     if (other_tc == env->current_tc)
-        env->active_tc.DSPControl = t0;
+        env->active_tc.DSPControl = arg1;
     else
-        env->tcs[other_tc].DSPControl = t0;
+        env->tcs[other_tc].DSPControl = arg1;
 }
 
 /* MIPS MT functions */
-target_ulong helper_dmt(target_ulong t0)
+target_ulong helper_dmt(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_emt(target_ulong t0)
+target_ulong helper_emt(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_dvpe(target_ulong t0)
+target_ulong helper_dvpe(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
 
-target_ulong helper_evpe(target_ulong t0)
+target_ulong helper_evpe(target_ulong arg1)
 {
     // TODO
-    t0 = 0;
-    // rt = t0
+    arg1 = 0;
+    // rt = arg1
 
-    return t0;
+    return arg1;
 }
 #endif /* !CONFIG_USER_ONLY */
 
-void helper_fork(target_ulong t0, target_ulong t1)
+void helper_fork(target_ulong arg1, target_ulong arg2)
 {
-    // t0 = rt, t1 = rs
-    t0 = 0;
+    // arg1 = rt, arg2 = rs
+    arg1 = 0;
     // TODO: store to TC register
 }
 
-target_ulong helper_yield(target_ulong t0)
+target_ulong helper_yield(target_ulong arg1)
 {
-    if (t0 < 0) {
+    if (arg1 < 0) {
         /* No scheduling policy implemented. */
-        if (t0 != -2) {
+        if (arg1 != -2) {
             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
@@ -1474,14 +1474,14 @@
                 helper_raise_exception(EXCP_THREAD);
             }
         }
-    } else if (t0 == 0) {
+    } else if (arg1 == 0) {
         if (0 /* TODO: TC underflow */) {
             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
             helper_raise_exception(EXCP_THREAD);
         } else {
             // TODO: Deallocate TC
         }
-    } else if (t0 > 0) {
+    } else if (arg1 > 0) {
         /* Yield qualifier inputs not implemented. */
         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
@@ -1884,53 +1884,53 @@
 
 target_ulong helper_cfc1 (uint32_t reg)
 {
-    target_ulong t0;
+    target_ulong arg1;
 
     switch (reg) {
     case 0:
-        t0 = (int32_t)env->active_fpu.fcr0;
+        arg1 = (int32_t)env->active_fpu.fcr0;
         break;
     case 25:
-        t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
+        arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
         break;
     case 26:
-        t0 = env->active_fpu.fcr31 & 0x0003f07c;
+        arg1 = env->active_fpu.fcr31 & 0x0003f07c;
         break;
     case 28:
-        t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
+        arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
         break;
     default:
-        t0 = (int32_t)env->active_fpu.fcr31;
+        arg1 = (int32_t)env->active_fpu.fcr31;
         break;
     }
 
-    return t0;
+    return arg1;
 }
 
-void helper_ctc1 (target_ulong t0, uint32_t reg)
+void helper_ctc1 (target_ulong arg1, uint32_t reg)
 {
     switch(reg) {
     case 25:
-        if (t0 & 0xffffff00)
+        if (arg1 & 0xffffff00)
             return;
-        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
-                     ((t0 & 0x1) << 23);
+        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
+                     ((arg1 & 0x1) << 23);
         break;
     case 26:
-        if (t0 & 0x007c0000)
+        if (arg1 & 0x007c0000)
             return;
-        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
+        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
         break;
     case 28:
-        if (t0 & 0x007c0000)
+        if (arg1 & 0x007c0000)
             return;
-        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
-                     ((t0 & 0x4) << 22);
+        env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
+                     ((arg1 & 0x4) << 22);
         break;
     case 31:
-        if (t0 & 0x007c0000)
+        if (arg1 & 0x007c0000)
             return;
-        env->active_fpu.fcr31 = t0;
+        env->active_fpu.fcr31 = arg1;
         break;
     default:
         return;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 514e989..a83a45d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -546,48 +546,48 @@
 /* Moves to/from shadow registers. */
 static inline void gen_load_srsgpr (int from, int to)
 {
-    TCGv r_tmp1 = tcg_temp_new();
+    TCGv t0 = tcg_temp_new();
 
     if (from == 0)
-        tcg_gen_movi_tl(r_tmp1, 0);
+        tcg_gen_movi_tl(t0, 0);
     else {
-        TCGv_i32 r_tmp2 = tcg_temp_new_i32();
+        TCGv_i32 t2 = tcg_temp_new_i32();
         TCGv_ptr addr = tcg_temp_new_ptr();
 
-        tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
-        tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
-        tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
-        tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
-        tcg_gen_ext_i32_ptr(addr, r_tmp2);
+        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
+        tcg_gen_andi_i32(t2, t2, 0xf);
+        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
+        tcg_gen_ext_i32_ptr(addr, t2);
         tcg_gen_add_ptr(addr, cpu_env, addr);
 
-        tcg_gen_ld_tl(r_tmp1, addr, sizeof(target_ulong) * from);
+        tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
         tcg_temp_free_ptr(addr);
-        tcg_temp_free_i32(r_tmp2);
+        tcg_temp_free_i32(t2);
     }
-    gen_store_gpr(r_tmp1, to);
-    tcg_temp_free(r_tmp1);
+    gen_store_gpr(t0, to);
+    tcg_temp_free(t0);
 }
 
 static inline void gen_store_srsgpr (int from, int to)
 {
     if (to != 0) {
-        TCGv r_tmp1 = tcg_temp_new();
-        TCGv_i32 r_tmp2 = tcg_temp_new_i32();
+        TCGv t0 = tcg_temp_new();
+        TCGv_i32 t2 = tcg_temp_new_i32();
         TCGv_ptr addr = tcg_temp_new_ptr();
 
-        gen_load_gpr(r_tmp1, from);
-        tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
-        tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
-        tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
-        tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
-        tcg_gen_ext_i32_ptr(addr, r_tmp2);
+        gen_load_gpr(t0, from);
+        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
+        tcg_gen_andi_i32(t2, t2, 0xf);
+        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
+        tcg_gen_ext_i32_ptr(addr, t2);
         tcg_gen_add_ptr(addr, cpu_env, addr);
 
-        tcg_gen_st_tl(r_tmp1, addr, sizeof(target_ulong) * to);
+        tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
         tcg_temp_free_ptr(addr);
-        tcg_temp_free_i32(r_tmp2);
-        tcg_temp_free(r_tmp1);
+        tcg_temp_free_i32(t2);
+        tcg_temp_free(t0);
     }
 }
 
@@ -887,10 +887,10 @@
 }
 
 /* load/store instructions. */
-#define OP_LD(insn,fname)                                        \
-static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx)    \
-{                                                                \
-    tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx);                  \
+#define OP_LD(insn,fname)                                                 \
+static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
+{                                                                         \
+    tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                        \
 }
 OP_LD(lb,ld8s);
 OP_LD(lbu,ld8u);
@@ -903,10 +903,10 @@
 #endif
 #undef OP_LD
 
-#define OP_ST(insn,fname)                                        \
-static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
-{                                                                \
-    tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx);                  \
+#define OP_ST(insn,fname)                                                  \
+static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
+{                                                                          \
+    tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx);                        \
 }
 OP_ST(sb,st8);
 OP_ST(sh,st16);
@@ -916,12 +916,14 @@
 #endif
 #undef OP_ST
 
-#define OP_LD_ATOMIC(insn,fname)                                        \
-static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx)  \
-{                                                                       \
-    tcg_gen_mov_tl(t1, t0);                                             \
-    tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx);                         \
-    tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr));         \
+#define OP_LD_ATOMIC(insn,fname)                                           \
+static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx)  \
+{                                                                          \
+    TCGv t0 = tcg_temp_new();                                              \
+    tcg_gen_mov_tl(t0, arg1);                                              \
+    tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                         \
+    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr));            \
+    tcg_temp_free(t0);                                                     \
 }
 OP_LD_ATOMIC(ll,ld32s);
 #if defined(TARGET_MIPS64)
@@ -929,28 +931,28 @@
 #endif
 #undef OP_LD_ATOMIC
 
-#define OP_ST_ATOMIC(insn,fname,almask)                                 \
-static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx)  \
-{                                                                       \
-    TCGv r_tmp = tcg_temp_new();                                        \
-    int l1 = gen_new_label();                                           \
-    int l2 = gen_new_label();                                           \
-    int l3 = gen_new_label();                                           \
-                                                                        \
-    tcg_gen_andi_tl(r_tmp, t0, almask);                                 \
-    tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1);                      \
-    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));       \
-    generate_exception(ctx, EXCP_AdES);                                 \
-    gen_set_label(l1);                                                  \
-    tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr));      \
-    tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2);                      \
-    tcg_temp_free(r_tmp);                                               \
-    tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx);                         \
-    tcg_gen_movi_tl(t0, 1);                                             \
-    tcg_gen_br(l3);                                                     \
-    gen_set_label(l2);                                                  \
-    tcg_gen_movi_tl(t0, 0);                                             \
-    gen_set_label(l3);                                                  \
+#define OP_ST_ATOMIC(insn,fname,almask)                                              \
+static inline void op_ldst_##insn(TCGv ret, TCGv arg1, TCGv arg2, DisasContext *ctx) \
+{                                                                                    \
+    TCGv t0 = tcg_temp_new();                                                        \
+    int l1 = gen_new_label();                                                        \
+    int l2 = gen_new_label();                                                        \
+    int l3 = gen_new_label();                                                        \
+                                                                                     \
+    tcg_gen_andi_tl(t0, arg2, almask);                                               \
+    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);                                      \
+    tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr));                  \
+    generate_exception(ctx, EXCP_AdES);                                              \
+    gen_set_label(l1);                                                               \
+    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr));                      \
+    tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2);                                    \
+    tcg_temp_free(t0);                                                               \
+    tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx);                                  \
+    tcg_gen_movi_tl(ret, 1);                                                         \
+    tcg_gen_br(l3);                                                                  \
+    gen_set_label(l2);                                                               \
+    tcg_gen_movi_tl(ret, 0);                                                         \
+    gen_set_label(l3);                                                               \
 }
 OP_ST_ATOMIC(sc,st32,0x3);
 #if defined(TARGET_MIPS64)
@@ -980,132 +982,132 @@
 #if defined(TARGET_MIPS64)
     case OPC_LWU:
         save_cpu_state(ctx, 0);
-        op_ldst_lwu(t0, ctx);
+        op_ldst_lwu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lwu";
         break;
     case OPC_LD:
         save_cpu_state(ctx, 0);
-        op_ldst_ld(t0, ctx);
+        op_ldst_ld(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "ld";
         break;
     case OPC_LLD:
         save_cpu_state(ctx, 0);
-        op_ldst_lld(t0, t1, ctx);
+        op_ldst_lld(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lld";
         break;
     case OPC_SD:
         save_cpu_state(ctx, 0);
         gen_load_gpr(t1, rt);
-        op_ldst_sd(t0, t1, ctx);
+        op_ldst_sd(t1, t0, ctx);
         opn = "sd";
         break;
     case OPC_LDL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_3i(ldl, t1, t0, t1, ctx->mem_idx);
+        gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
         opn = "ldl";
         break;
     case OPC_SDL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_2i(sdl, t0, t1, ctx->mem_idx);
+        gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
         opn = "sdl";
         break;
     case OPC_LDR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_3i(ldr, t1, t0, t1, ctx->mem_idx);
+        gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
         opn = "ldr";
         break;
     case OPC_SDR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_2i(sdr, t0, t1, ctx->mem_idx);
+        gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
         opn = "sdr";
         break;
 #endif
     case OPC_LW:
         save_cpu_state(ctx, 0);
-        op_ldst_lw(t0, ctx);
+        op_ldst_lw(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lw";
         break;
     case OPC_SW:
         save_cpu_state(ctx, 0);
         gen_load_gpr(t1, rt);
-        op_ldst_sw(t0, t1, ctx);
+        op_ldst_sw(t1, t0, ctx);
         opn = "sw";
         break;
     case OPC_LH:
         save_cpu_state(ctx, 0);
-        op_ldst_lh(t0, ctx);
+        op_ldst_lh(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lh";
         break;
     case OPC_SH:
         save_cpu_state(ctx, 0);
         gen_load_gpr(t1, rt);
-        op_ldst_sh(t0, t1, ctx);
+        op_ldst_sh(t1, t0, ctx);
         opn = "sh";
         break;
     case OPC_LHU:
         save_cpu_state(ctx, 0);
-        op_ldst_lhu(t0, ctx);
+        op_ldst_lhu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lhu";
         break;
     case OPC_LB:
         save_cpu_state(ctx, 0);
-        op_ldst_lb(t0, ctx);
+        op_ldst_lb(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lb";
         break;
     case OPC_SB:
         save_cpu_state(ctx, 0);
         gen_load_gpr(t1, rt);
-        op_ldst_sb(t0, t1, ctx);
+        op_ldst_sb(t1, t0, ctx);
         opn = "sb";
         break;
     case OPC_LBU:
         save_cpu_state(ctx, 0);
-        op_ldst_lbu(t0, ctx);
+        op_ldst_lbu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lbu";
         break;
     case OPC_LWL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
+        gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
         opn = "lwl";
         break;
     case OPC_SWL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_2i(swl, t0, t1, ctx->mem_idx);
+        gen_helper_2i(swl, t1, t0, ctx->mem_idx);
         opn = "swr";
         break;
     case OPC_LWR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
+        gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
         opn = "lwr";
         break;
     case OPC_SWR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
-        gen_helper_2i(swr, t0, t1, ctx->mem_idx);
+        gen_helper_2i(swr, t1, t0, ctx->mem_idx);
         opn = "swr";
         break;
     case OPC_LL:
         save_cpu_state(ctx, 0);
-        op_ldst_ll(t0, t1, ctx);
+        op_ldst_ll(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "ll";
         break;
@@ -1141,13 +1143,13 @@
 #if defined(TARGET_MIPS64)
     case OPC_SCD:
         save_cpu_state(ctx, 0);
-        op_ldst_scd(t0, t1, ctx);
+        op_ldst_scd(t0, t1, t0, ctx);
         opn = "scd";
         break;
 #endif
     case OPC_SC:
         save_cpu_state(ctx, 0);
-        op_ldst_sc(t0, t1, ctx);
+        op_ldst_sc(t0, t1, t0, ctx);
         opn = "sc";
         break;
     }
@@ -1430,12 +1432,12 @@
             /* rotr is decoded as srl on non-R2 CPUs */
             if (env->insn_flags & ISA_MIPS32R2) {
                 if (uimm != 0) {
-                    TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+                    TCGv_i32 t1 = tcg_temp_new_i32();
 
-                    tcg_gen_trunc_tl_i32(r_tmp1, t0);
-                    tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm);
-                    tcg_gen_ext_i32_tl(cpu_gpr[rt], r_tmp1);
-                    tcg_temp_free_i32(r_tmp1);
+                    tcg_gen_trunc_tl_i32(t1, t0);
+                    tcg_gen_rotri_i32(t1, t1, uimm);
+                    tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
+                    tcg_temp_free_i32(t1);
                 }
                 opn = "rotr";
             } else {
@@ -2840,37 +2842,37 @@
 
 #ifndef CONFIG_USER_ONLY
 /* CP0 (MMU and control) */
-static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
+static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
 {
-    TCGv_i32 r_tmp = tcg_temp_new_i32();
+    TCGv_i32 t0 = tcg_temp_new_i32();
 
-    tcg_gen_ld_i32(r_tmp, cpu_env, off);
-    tcg_gen_ext_i32_tl(t, r_tmp);
-    tcg_temp_free_i32(r_tmp);
+    tcg_gen_ld_i32(t0, cpu_env, off);
+    tcg_gen_ext_i32_tl(arg, t0);
+    tcg_temp_free_i32(t0);
 }
 
-static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
+static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
 {
-    tcg_gen_ld_tl(t, cpu_env, off);
-    tcg_gen_ext32s_tl(t, t);
+    tcg_gen_ld_tl(arg, cpu_env, off);
+    tcg_gen_ext32s_tl(arg, arg);
 }
 
-static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
+static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
 {
-    TCGv_i32 r_tmp = tcg_temp_new_i32();
+    TCGv_i32 t0 = tcg_temp_new_i32();
 
-    tcg_gen_trunc_tl_i32(r_tmp, t);
-    tcg_gen_st_i32(r_tmp, cpu_env, off);
-    tcg_temp_free_i32(r_tmp);
+    tcg_gen_trunc_tl_i32(t0, arg);
+    tcg_gen_st_i32(t0, cpu_env, off);
+    tcg_temp_free_i32(t0);
 }
 
-static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
+static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
 {
-    tcg_gen_ext32s_tl(t, t);
-    tcg_gen_st_tl(t, cpu_env, off);
+    tcg_gen_ext32s_tl(arg, arg);
+    tcg_gen_st_tl(arg, cpu_env, off);
 }
 
-static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -2881,22 +2883,22 @@
     case 0:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
             rn = "Index";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_mvpcontrol(t0);
+            gen_helper_mfc0_mvpcontrol(arg);
             rn = "MVPControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_mvpconf0(t0);
+            gen_helper_mfc0_mvpconf0(arg);
             rn = "MVPConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_mvpconf1(t0);
+            gen_helper_mfc0_mvpconf1(arg);
             rn = "MVPConf1";
             break;
         default:
@@ -2906,42 +2908,42 @@
     case 1:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_random(t0);
+            gen_helper_mfc0_random(arg);
             rn = "Random";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
             rn = "VPEControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
             rn = "VPEConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
             rn = "VPEConf1";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load64(t0, offsetof(CPUState, CP0_YQMask));
+            gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
             rn = "YQMask";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPESchedule));
+            gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPEScheFBack));
+            gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
             rn = "VPEOpt";
             break;
         default:
@@ -2951,43 +2953,43 @@
     case 2:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "EntryLo0";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tcstatus(t0);
+            gen_helper_mfc0_tcstatus(arg);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tcbind(t0);
+            gen_helper_mfc0_tcbind(arg);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tcrestart(t0);
+            gen_helper_mfc0_tcrestart(arg);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tchalt(t0);
+            gen_helper_mfc0_tchalt(arg);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tccontext(t0);
+            gen_helper_mfc0_tccontext(arg);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tcschedule(t0);
+            gen_helper_mfc0_tcschedule(arg);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tcschefback(t0);
+            gen_helper_mfc0_tcschefback(arg);
             rn = "TCScheFBack";
             break;
         default:
@@ -2997,8 +2999,8 @@
     case 3:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "EntryLo1";
             break;
         default:
@@ -3008,12 +3010,12 @@
     case 4:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "Context";
             break;
         case 1:
-//            gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
+//            gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //            break;
         default:
@@ -3023,12 +3025,12 @@
     case 5:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
             rn = "PageMask";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
             rn = "PageGrain";
             break;
         default:
@@ -3038,32 +3040,32 @@
     case 6:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
             rn = "Wired";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
             rn = "SRSConf4";
             break;
         default:
@@ -3074,7 +3076,7 @@
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
             rn = "HWREna";
             break;
         default:
@@ -3084,8 +3086,8 @@
     case 8:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "BadVAddr";
             break;
         default:
@@ -3098,7 +3100,7 @@
             /* Mark as an IO operation because we read the time.  */
             if (use_icount)
                 gen_io_start();
-            gen_helper_mfc0_count(t0);
+            gen_helper_mfc0_count(arg);
             if (use_icount) {
                 gen_io_end();
                 ctx->bstate = BS_STOP;
@@ -3113,8 +3115,8 @@
     case 10:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "EntryHi";
             break;
         default:
@@ -3124,7 +3126,7 @@
     case 11:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -3135,22 +3137,22 @@
     case 12:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
             rn = "Status";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
             rn = "IntCtl";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
             rn = "SRSCtl";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
             rn = "SRSMap";
             break;
         default:
@@ -3160,7 +3162,7 @@
     case 13:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
             rn = "Cause";
             break;
         default:
@@ -3170,8 +3172,8 @@
     case 14:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "EPC";
             break;
         default:
@@ -3181,12 +3183,12 @@
     case 15:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
             rn = "PRid";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
             rn = "EBase";
             break;
         default:
@@ -3196,29 +3198,29 @@
     case 16:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
             rn = "Config";
             break;
         case 1:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
             rn = "Config1";
             break;
         case 2:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
             rn = "Config2";
             break;
         case 3:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
             rn = "Config3";
             break;
         /* 4,5 are reserved */
         /* 6,7 are implementation dependent */
         case 6:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
             rn = "Config6";
             break;
         case 7:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
             rn = "Config7";
             break;
         default:
@@ -3228,7 +3230,7 @@
     case 17:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_lladdr(t0);
+            gen_helper_mfc0_lladdr(arg);
             rn = "LLAddr";
             break;
         default:
@@ -3238,7 +3240,7 @@
     case 18:
         switch (sel) {
         case 0 ... 7:
-            gen_helper_1i(mfc0_watchlo, t0, sel);
+            gen_helper_1i(mfc0_watchlo, arg, sel);
             rn = "WatchLo";
             break;
         default:
@@ -3248,7 +3250,7 @@
     case 19:
         switch (sel) {
         case 0 ...7:
-            gen_helper_1i(mfc0_watchhi, t0, sel);
+            gen_helper_1i(mfc0_watchhi, arg, sel);
             rn = "WatchHi";
             break;
         default:
@@ -3260,8 +3262,8 @@
         case 0:
 #if defined(TARGET_MIPS64)
             check_insn(env, ctx, ISA_MIPS3);
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "XContext";
             break;
 #endif
@@ -3273,7 +3275,7 @@
        /* Officially reserved, but sel 0 is used for R1x000 framemask */
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
             rn = "Framemask";
             break;
         default:
@@ -3281,29 +3283,29 @@
         }
         break;
     case 22:
-        tcg_gen_movi_tl(t0, 0); /* unimplemented */
+        tcg_gen_movi_tl(arg, 0); /* unimplemented */
         rn = "'Diagnostic"; /* implementation dependent */
         break;
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_debug(t0); /* EJTAG support */
+            gen_helper_mfc0_debug(arg); /* EJTAG support */
             rn = "Debug";
             break;
         case 1:
-//            gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
+//            gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
             rn = "TraceControl";
 //            break;
         case 2:
-//            gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
+//            gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
             rn = "TraceControl2";
 //            break;
         case 3:
-//            gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
+//            gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
             rn = "UserTraceData";
 //            break;
         case 4:
-//            gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
+//            gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
             rn = "TraceBPC";
 //            break;
         default:
@@ -3314,8 +3316,8 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "DEPC";
             break;
         default:
@@ -3325,35 +3327,35 @@
     case 25:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
             rn = "Performance0";
             break;
         case 1:
-//            gen_helper_mfc0_performance1(t0);
+//            gen_helper_mfc0_performance1(arg);
             rn = "Performance1";
 //            break;
         case 2:
-//            gen_helper_mfc0_performance2(t0);
+//            gen_helper_mfc0_performance2(arg);
             rn = "Performance2";
 //            break;
         case 3:
-//            gen_helper_mfc0_performance3(t0);
+//            gen_helper_mfc0_performance3(arg);
             rn = "Performance3";
 //            break;
         case 4:
-//            gen_helper_mfc0_performance4(t0);
+//            gen_helper_mfc0_performance4(arg);
             rn = "Performance4";
 //            break;
         case 5:
-//            gen_helper_mfc0_performance5(t0);
+//            gen_helper_mfc0_performance5(arg);
             rn = "Performance5";
 //            break;
         case 6:
-//            gen_helper_mfc0_performance6(t0);
+//            gen_helper_mfc0_performance6(arg);
             rn = "Performance6";
 //            break;
         case 7:
-//            gen_helper_mfc0_performance7(t0);
+//            gen_helper_mfc0_performance7(arg);
             rn = "Performance7";
 //            break;
         default:
@@ -3361,13 +3363,13 @@
         }
         break;
     case 26:
-        tcg_gen_movi_tl(t0, 0); /* unimplemented */
+        tcg_gen_movi_tl(arg, 0); /* unimplemented */
         rn = "ECC";
         break;
     case 27:
         switch (sel) {
         case 0 ... 3:
-            tcg_gen_movi_tl(t0, 0); /* unimplemented */
+            tcg_gen_movi_tl(arg, 0); /* unimplemented */
             rn = "CacheErr";
             break;
         default:
@@ -3380,14 +3382,14 @@
         case 2:
         case 4:
         case 6:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
             rn = "DataLo";
             break;
         default:
@@ -3400,14 +3402,14 @@
         case 2:
         case 4:
         case 6:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
             rn = "DataHi";
             break;
         default:
@@ -3417,8 +3419,8 @@
     case 30:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
-            tcg_gen_ext32s_tl(t0, t0);
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+            tcg_gen_ext32s_tl(arg, arg);
             rn = "ErrorEPC";
             break;
         default:
@@ -3429,7 +3431,7 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
             rn = "DESAVE";
             break;
         default:
@@ -3447,7 +3449,7 @@
     generate_exception(ctx, EXCP_RI);
 }
 
-static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -3461,12 +3463,12 @@
     case 0:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_index(t0);
+            gen_helper_mtc0_index(arg);
             rn = "Index";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_mvpcontrol(t0);
+            gen_helper_mtc0_mvpcontrol(arg);
             rn = "MVPControl";
             break;
         case 2:
@@ -3491,37 +3493,37 @@
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpecontrol(t0);
+            gen_helper_mtc0_vpecontrol(arg);
             rn = "VPEControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpeconf0(t0);
+            gen_helper_mtc0_vpeconf0(arg);
             rn = "VPEConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpeconf1(t0);
+            gen_helper_mtc0_vpeconf1(arg);
             rn = "VPEConf1";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_yqmask(t0);
+            gen_helper_mtc0_yqmask(arg);
             rn = "YQMask";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPESchedule));
+            gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPEScheFBack));
+            gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpeopt(t0);
+            gen_helper_mtc0_vpeopt(arg);
             rn = "VPEOpt";
             break;
         default:
@@ -3531,42 +3533,42 @@
     case 2:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entrylo0(t0);
+            gen_helper_mtc0_entrylo0(arg);
             rn = "EntryLo0";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcstatus(t0);
+            gen_helper_mtc0_tcstatus(arg);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcbind(t0);
+            gen_helper_mtc0_tcbind(arg);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcrestart(t0);
+            gen_helper_mtc0_tcrestart(arg);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tchalt(t0);
+            gen_helper_mtc0_tchalt(arg);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tccontext(t0);
+            gen_helper_mtc0_tccontext(arg);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcschedule(t0);
+            gen_helper_mtc0_tcschedule(arg);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcschefback(t0);
+            gen_helper_mtc0_tcschefback(arg);
             rn = "TCScheFBack";
             break;
         default:
@@ -3576,7 +3578,7 @@
     case 3:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entrylo1(t0);
+            gen_helper_mtc0_entrylo1(arg);
             rn = "EntryLo1";
             break;
         default:
@@ -3586,11 +3588,11 @@
     case 4:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_context(t0);
+            gen_helper_mtc0_context(arg);
             rn = "Context";
             break;
         case 1:
-//            gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
+//            gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //            break;
         default:
@@ -3600,12 +3602,12 @@
     case 5:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_pagemask(t0);
+            gen_helper_mtc0_pagemask(arg);
             rn = "PageMask";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_pagegrain(t0);
+            gen_helper_mtc0_pagegrain(arg);
             rn = "PageGrain";
             break;
         default:
@@ -3615,32 +3617,32 @@
     case 6:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_wired(t0);
+            gen_helper_mtc0_wired(arg);
             rn = "Wired";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf0(t0);
+            gen_helper_mtc0_srsconf0(arg);
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf1(t0);
+            gen_helper_mtc0_srsconf1(arg);
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf2(t0);
+            gen_helper_mtc0_srsconf2(arg);
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf3(t0);
+            gen_helper_mtc0_srsconf3(arg);
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf4(t0);
+            gen_helper_mtc0_srsconf4(arg);
             rn = "SRSConf4";
             break;
         default:
@@ -3651,7 +3653,7 @@
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_hwrena(t0);
+            gen_helper_mtc0_hwrena(arg);
             rn = "HWREna";
             break;
         default:
@@ -3665,7 +3667,7 @@
     case 9:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_count(t0);
+            gen_helper_mtc0_count(arg);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -3676,7 +3678,7 @@
     case 10:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entryhi(t0);
+            gen_helper_mtc0_entryhi(arg);
             rn = "EntryHi";
             break;
         default:
@@ -3686,7 +3688,7 @@
     case 11:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_compare(t0);
+            gen_helper_mtc0_compare(arg);
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -3698,7 +3700,7 @@
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_status(t0);
+            gen_helper_mtc0_status(arg);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
@@ -3706,21 +3708,21 @@
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_intctl(t0);
+            gen_helper_mtc0_intctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "IntCtl";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsctl(t0);
+            gen_helper_mtc0_srsctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSCtl";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
+            gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSMap";
@@ -3733,7 +3735,7 @@
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_cause(t0);
+            gen_helper_mtc0_cause(arg);
             rn = "Cause";
             break;
         default:
@@ -3743,7 +3745,7 @@
     case 14:
         switch (sel) {
         case 0:
-            gen_mtc0_store64(t0, offsetof(CPUState, CP0_EPC));
+            gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
             rn = "EPC";
             break;
         default:
@@ -3758,7 +3760,7 @@
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_ebase(t0);
+            gen_helper_mtc0_ebase(arg);
             rn = "EBase";
             break;
         default:
@@ -3768,7 +3770,7 @@
     case 16:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_config0(t0);
+            gen_helper_mtc0_config0(arg);
             rn = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -3778,7 +3780,7 @@
             rn = "Config1";
             break;
         case 2:
-            gen_helper_mtc0_config2(t0);
+            gen_helper_mtc0_config2(arg);
             rn = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -3815,7 +3817,7 @@
     case 18:
         switch (sel) {
         case 0 ... 7:
-            gen_helper_1i(mtc0_watchlo, t0, sel);
+            gen_helper_1i(mtc0_watchlo, arg, sel);
             rn = "WatchLo";
             break;
         default:
@@ -3825,7 +3827,7 @@
     case 19:
         switch (sel) {
         case 0 ... 7:
-            gen_helper_1i(mtc0_watchhi, t0, sel);
+            gen_helper_1i(mtc0_watchhi, arg, sel);
             rn = "WatchHi";
             break;
         default:
@@ -3837,7 +3839,7 @@
         case 0:
 #if defined(TARGET_MIPS64)
             check_insn(env, ctx, ISA_MIPS3);
-            gen_helper_mtc0_xcontext(t0);
+            gen_helper_mtc0_xcontext(arg);
             rn = "XContext";
             break;
 #endif
@@ -3849,7 +3851,7 @@
        /* Officially reserved, but sel 0 is used for R1x000 framemask */
         switch (sel) {
         case 0:
-            gen_helper_mtc0_framemask(t0);
+            gen_helper_mtc0_framemask(arg);
             rn = "Framemask";
             break;
         default:
@@ -3863,20 +3865,20 @@
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_debug(t0); /* EJTAG support */
+            gen_helper_mtc0_debug(arg); /* EJTAG support */
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
             rn = "Debug";
             break;
         case 1:
-//            gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
             rn = "TraceControl";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            break;
         case 2:
-//            gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
             rn = "TraceControl2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -3884,13 +3886,13 @@
         case 3:
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-//            gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
+//            gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
             rn = "UserTraceData";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            break;
         case 4:
-//            gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
+//            gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceBPC";
@@ -3903,7 +3905,7 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            gen_mtc0_store64(t0, offsetof(CPUState, CP0_DEPC));
+            gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
             rn = "DEPC";
             break;
         default:
@@ -3913,35 +3915,35 @@
     case 25:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_performance0(t0);
+            gen_helper_mtc0_performance0(arg);
             rn = "Performance0";
             break;
         case 1:
-//            gen_helper_mtc0_performance1(t0);
+//            gen_helper_mtc0_performance1(arg);
             rn = "Performance1";
 //            break;
         case 2:
-//            gen_helper_mtc0_performance2(t0);
+//            gen_helper_mtc0_performance2(arg);
             rn = "Performance2";
 //            break;
         case 3:
-//            gen_helper_mtc0_performance3(t0);
+//            gen_helper_mtc0_performance3(arg);
             rn = "Performance3";
 //            break;
         case 4:
-//            gen_helper_mtc0_performance4(t0);
+//            gen_helper_mtc0_performance4(arg);
             rn = "Performance4";
 //            break;
         case 5:
-//            gen_helper_mtc0_performance5(t0);
+//            gen_helper_mtc0_performance5(arg);
             rn = "Performance5";
 //            break;
         case 6:
-//            gen_helper_mtc0_performance6(t0);
+//            gen_helper_mtc0_performance6(arg);
             rn = "Performance6";
 //            break;
         case 7:
-//            gen_helper_mtc0_performance7(t0);
+//            gen_helper_mtc0_performance7(arg);
             rn = "Performance7";
 //            break;
         default:
@@ -3968,14 +3970,14 @@
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taglo(t0);
+            gen_helper_mtc0_taglo(arg);
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datalo(t0);
+            gen_helper_mtc0_datalo(arg);
             rn = "DataLo";
             break;
         default:
@@ -3988,14 +3990,14 @@
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taghi(t0);
+            gen_helper_mtc0_taghi(arg);
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datahi(t0);
+            gen_helper_mtc0_datahi(arg);
             rn = "DataHi";
             break;
         default:
@@ -4006,7 +4008,7 @@
     case 30:
         switch (sel) {
         case 0:
-            gen_mtc0_store64(t0, offsetof(CPUState, CP0_ErrorEPC));
+            gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
             rn = "ErrorEPC";
             break;
         default:
@@ -4017,7 +4019,7 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
+            gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
             rn = "DESAVE";
             break;
         default:
@@ -4043,7 +4045,7 @@
 }
 
 #if defined(TARGET_MIPS64)
-static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -4054,22 +4056,22 @@
     case 0:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
             rn = "Index";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_mvpcontrol(t0);
+            gen_helper_mfc0_mvpcontrol(arg);
             rn = "MVPControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_mvpconf0(t0);
+            gen_helper_mfc0_mvpconf0(arg);
             rn = "MVPConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_mvpconf1(t0);
+            gen_helper_mfc0_mvpconf1(arg);
             rn = "MVPConf1";
             break;
         default:
@@ -4079,42 +4081,42 @@
     case 1:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_random(t0);
+            gen_helper_mfc0_random(arg);
             rn = "Random";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
             rn = "VPEControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
             rn = "VPEConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
             rn = "VPEConf1";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_YQMask));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
             rn = "YQMask";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
             rn = "VPEOpt";
             break;
         default:
@@ -4124,42 +4126,42 @@
     case 2:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
             rn = "EntryLo0";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tcstatus(t0);
+            gen_helper_mfc0_tcstatus(arg);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mfc0_tcbind(t0);
+            gen_helper_mfc0_tcbind(arg);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_dmfc0_tcrestart(t0);
+            gen_helper_dmfc0_tcrestart(arg);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_dmfc0_tchalt(t0);
+            gen_helper_dmfc0_tchalt(arg);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_dmfc0_tccontext(t0);
+            gen_helper_dmfc0_tccontext(arg);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_dmfc0_tcschedule(t0);
+            gen_helper_dmfc0_tcschedule(arg);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_dmfc0_tcschefback(t0);
+            gen_helper_dmfc0_tcschefback(arg);
             rn = "TCScheFBack";
             break;
         default:
@@ -4169,7 +4171,7 @@
     case 3:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
             rn = "EntryLo1";
             break;
         default:
@@ -4179,11 +4181,11 @@
     case 4:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
             rn = "Context";
             break;
         case 1:
-//            gen_helper_dmfc0_contextconfig(t0); /* SmartMIPS ASE */
+//            gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //            break;
         default:
@@ -4193,12 +4195,12 @@
     case 5:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
             rn = "PageMask";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
             rn = "PageGrain";
             break;
         default:
@@ -4208,32 +4210,32 @@
     case 6:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
             rn = "Wired";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
             rn = "SRSConf4";
             break;
         default:
@@ -4244,7 +4246,7 @@
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
             rn = "HWREna";
             break;
         default:
@@ -4254,7 +4256,7 @@
     case 8:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
             rn = "BadVAddr";
             break;
         default:
@@ -4267,7 +4269,7 @@
             /* Mark as an IO operation because we read the time.  */
             if (use_icount)
                 gen_io_start();
-            gen_helper_mfc0_count(t0);
+            gen_helper_mfc0_count(arg);
             if (use_icount) {
                 gen_io_end();
                 ctx->bstate = BS_STOP;
@@ -4282,7 +4284,7 @@
     case 10:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
             rn = "EntryHi";
             break;
         default:
@@ -4292,7 +4294,7 @@
     case 11:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -4303,22 +4305,22 @@
     case 12:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
             rn = "Status";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
             rn = "IntCtl";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
             rn = "SRSCtl";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
             rn = "SRSMap";
             break;
         default:
@@ -4328,7 +4330,7 @@
     case 13:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
             rn = "Cause";
             break;
         default:
@@ -4338,7 +4340,7 @@
     case 14:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
             rn = "EPC";
             break;
         default:
@@ -4348,12 +4350,12 @@
     case 15:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
             rn = "PRid";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
             rn = "EBase";
             break;
         default:
@@ -4363,28 +4365,28 @@
     case 16:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
             rn = "Config";
             break;
         case 1:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
             rn = "Config1";
             break;
         case 2:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
             rn = "Config2";
             break;
         case 3:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
             rn = "Config3";
             break;
        /* 6,7 are implementation dependent */
         case 6:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
             rn = "Config6";
             break;
         case 7:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
             rn = "Config7";
             break;
         default:
@@ -4394,7 +4396,7 @@
     case 17:
         switch (sel) {
         case 0:
-            gen_helper_dmfc0_lladdr(t0);
+            gen_helper_dmfc0_lladdr(arg);
             rn = "LLAddr";
             break;
         default:
@@ -4404,7 +4406,7 @@
     case 18:
         switch (sel) {
         case 0 ... 7:
-            gen_helper_1i(dmfc0_watchlo, t0, sel);
+            gen_helper_1i(dmfc0_watchlo, arg, sel);
             rn = "WatchLo";
             break;
         default:
@@ -4414,7 +4416,7 @@
     case 19:
         switch (sel) {
         case 0 ... 7:
-            gen_helper_1i(mfc0_watchhi, t0, sel);
+            gen_helper_1i(mfc0_watchhi, arg, sel);
             rn = "WatchHi";
             break;
         default:
@@ -4425,7 +4427,7 @@
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS3);
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
             rn = "XContext";
             break;
         default:
@@ -4436,7 +4438,7 @@
        /* Officially reserved, but sel 0 is used for R1x000 framemask */
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
             rn = "Framemask";
             break;
         default:
@@ -4444,29 +4446,29 @@
         }
         break;
     case 22:
-        tcg_gen_movi_tl(t0, 0); /* unimplemented */
+        tcg_gen_movi_tl(arg, 0); /* unimplemented */
         rn = "'Diagnostic"; /* implementation dependent */
         break;
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_debug(t0); /* EJTAG support */
+            gen_helper_mfc0_debug(arg); /* EJTAG support */
             rn = "Debug";
             break;
         case 1:
-//            gen_helper_dmfc0_tracecontrol(t0); /* PDtrace support */
+//            gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
             rn = "TraceControl";
 //            break;
         case 2:
-//            gen_helper_dmfc0_tracecontrol2(t0); /* PDtrace support */
+//            gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
             rn = "TraceControl2";
 //            break;
         case 3:
-//            gen_helper_dmfc0_usertracedata(t0); /* PDtrace support */
+//            gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
             rn = "UserTraceData";
 //            break;
         case 4:
-//            gen_helper_dmfc0_tracebpc(t0); /* PDtrace support */
+//            gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
             rn = "TraceBPC";
 //            break;
         default:
@@ -4477,7 +4479,7 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
             rn = "DEPC";
             break;
         default:
@@ -4487,35 +4489,35 @@
     case 25:
         switch (sel) {
         case 0:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
             rn = "Performance0";
             break;
         case 1:
-//            gen_helper_dmfc0_performance1(t0);
+//            gen_helper_dmfc0_performance1(arg);
             rn = "Performance1";
 //            break;
         case 2:
-//            gen_helper_dmfc0_performance2(t0);
+//            gen_helper_dmfc0_performance2(arg);
             rn = "Performance2";
 //            break;
         case 3:
-//            gen_helper_dmfc0_performance3(t0);
+//            gen_helper_dmfc0_performance3(arg);
             rn = "Performance3";
 //            break;
         case 4:
-//            gen_helper_dmfc0_performance4(t0);
+//            gen_helper_dmfc0_performance4(arg);
             rn = "Performance4";
 //            break;
         case 5:
-//            gen_helper_dmfc0_performance5(t0);
+//            gen_helper_dmfc0_performance5(arg);
             rn = "Performance5";
 //            break;
         case 6:
-//            gen_helper_dmfc0_performance6(t0);
+//            gen_helper_dmfc0_performance6(arg);
             rn = "Performance6";
 //            break;
         case 7:
-//            gen_helper_dmfc0_performance7(t0);
+//            gen_helper_dmfc0_performance7(arg);
             rn = "Performance7";
 //            break;
         default:
@@ -4523,14 +4525,14 @@
         }
         break;
     case 26:
-        tcg_gen_movi_tl(t0, 0); /* unimplemented */
+        tcg_gen_movi_tl(arg, 0); /* unimplemented */
         rn = "ECC";
         break;
     case 27:
         switch (sel) {
         /* ignored */
         case 0 ... 3:
-            tcg_gen_movi_tl(t0, 0); /* unimplemented */
+            tcg_gen_movi_tl(arg, 0); /* unimplemented */
             rn = "CacheErr";
             break;
         default:
@@ -4543,14 +4545,14 @@
         case 2:
         case 4:
         case 6:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
             rn = "DataLo";
             break;
         default:
@@ -4563,14 +4565,14 @@
         case 2:
         case 4:
         case 6:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
             rn = "DataHi";
             break;
         default:
@@ -4580,7 +4582,7 @@
     case 30:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
             rn = "ErrorEPC";
             break;
         default:
@@ -4591,7 +4593,7 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
+            gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
             rn = "DESAVE";
             break;
         default:
@@ -4609,7 +4611,7 @@
     generate_exception(ctx, EXCP_RI);
 }
 
-static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -4623,12 +4625,12 @@
     case 0:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_index(t0);
+            gen_helper_mtc0_index(arg);
             rn = "Index";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_mvpcontrol(t0);
+            gen_helper_mtc0_mvpcontrol(arg);
             rn = "MVPControl";
             break;
         case 2:
@@ -4653,37 +4655,37 @@
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpecontrol(t0);
+            gen_helper_mtc0_vpecontrol(arg);
             rn = "VPEControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpeconf0(t0);
+            gen_helper_mtc0_vpeconf0(arg);
             rn = "VPEConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpeconf1(t0);
+            gen_helper_mtc0_vpeconf1(arg);
             rn = "VPEConf1";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_yqmask(t0);
+            gen_helper_mtc0_yqmask(arg);
             rn = "YQMask";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+            tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+            tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_vpeopt(t0);
+            gen_helper_mtc0_vpeopt(arg);
             rn = "VPEOpt";
             break;
         default:
@@ -4693,42 +4695,42 @@
     case 2:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entrylo0(t0);
+            gen_helper_mtc0_entrylo0(arg);
             rn = "EntryLo0";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcstatus(t0);
+            gen_helper_mtc0_tcstatus(arg);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcbind(t0);
+            gen_helper_mtc0_tcbind(arg);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcrestart(t0);
+            gen_helper_mtc0_tcrestart(arg);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tchalt(t0);
+            gen_helper_mtc0_tchalt(arg);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tccontext(t0);
+            gen_helper_mtc0_tccontext(arg);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcschedule(t0);
+            gen_helper_mtc0_tcschedule(arg);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            gen_helper_mtc0_tcschefback(t0);
+            gen_helper_mtc0_tcschefback(arg);
             rn = "TCScheFBack";
             break;
         default:
@@ -4738,7 +4740,7 @@
     case 3:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entrylo1(t0);
+            gen_helper_mtc0_entrylo1(arg);
             rn = "EntryLo1";
             break;
         default:
@@ -4748,11 +4750,11 @@
     case 4:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_context(t0);
+            gen_helper_mtc0_context(arg);
             rn = "Context";
             break;
         case 1:
-//           gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
+//           gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //           break;
         default:
@@ -4762,12 +4764,12 @@
     case 5:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_pagemask(t0);
+            gen_helper_mtc0_pagemask(arg);
             rn = "PageMask";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_pagegrain(t0);
+            gen_helper_mtc0_pagegrain(arg);
             rn = "PageGrain";
             break;
         default:
@@ -4777,32 +4779,32 @@
     case 6:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_wired(t0);
+            gen_helper_mtc0_wired(arg);
             rn = "Wired";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf0(t0);
+            gen_helper_mtc0_srsconf0(arg);
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf1(t0);
+            gen_helper_mtc0_srsconf1(arg);
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf2(t0);
+            gen_helper_mtc0_srsconf2(arg);
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf3(t0);
+            gen_helper_mtc0_srsconf3(arg);
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf4(t0);
+            gen_helper_mtc0_srsconf4(arg);
             rn = "SRSConf4";
             break;
         default:
@@ -4813,7 +4815,7 @@
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_hwrena(t0);
+            gen_helper_mtc0_hwrena(arg);
             rn = "HWREna";
             break;
         default:
@@ -4827,7 +4829,7 @@
     case 9:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_count(t0);
+            gen_helper_mtc0_count(arg);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -4840,7 +4842,7 @@
     case 10:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entryhi(t0);
+            gen_helper_mtc0_entryhi(arg);
             rn = "EntryHi";
             break;
         default:
@@ -4850,7 +4852,7 @@
     case 11:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_compare(t0);
+            gen_helper_mtc0_compare(arg);
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -4864,7 +4866,7 @@
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_status(t0);
+            gen_helper_mtc0_status(arg);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
@@ -4872,21 +4874,21 @@
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_intctl(t0);
+            gen_helper_mtc0_intctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "IntCtl";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsctl(t0);
+            gen_helper_mtc0_srsctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSCtl";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
+            gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSMap";
@@ -4899,7 +4901,7 @@
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_cause(t0);
+            gen_helper_mtc0_cause(arg);
             rn = "Cause";
             break;
         default:
@@ -4909,7 +4911,7 @@
     case 14:
         switch (sel) {
         case 0:
-            tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
+            tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
             rn = "EPC";
             break;
         default:
@@ -4924,7 +4926,7 @@
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_ebase(t0);
+            gen_helper_mtc0_ebase(arg);
             rn = "EBase";
             break;
         default:
@@ -4934,7 +4936,7 @@
     case 16:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_config0(t0);
+            gen_helper_mtc0_config0(arg);
             rn = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -4944,7 +4946,7 @@
             rn = "Config1";
             break;
         case 2:
-            gen_helper_mtc0_config2(t0);
+            gen_helper_mtc0_config2(arg);
             rn = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -4972,7 +4974,7 @@
     case 18:
         switch (sel) {
         case 0 ... 7:
-            gen_helper_1i(mtc0_watchlo, t0, sel);
+            gen_helper_1i(mtc0_watchlo, arg, sel);
             rn = "WatchLo";
             break;
         default:
@@ -4982,7 +4984,7 @@
     case 19:
         switch (sel) {
         case 0 ... 7:
-            gen_helper_1i(mtc0_watchhi, t0, sel);
+            gen_helper_1i(mtc0_watchhi, arg, sel);
             rn = "WatchHi";
             break;
         default:
@@ -4993,7 +4995,7 @@
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS3);
-            gen_helper_mtc0_xcontext(t0);
+            gen_helper_mtc0_xcontext(arg);
             rn = "XContext";
             break;
         default:
@@ -5004,7 +5006,7 @@
        /* Officially reserved, but sel 0 is used for R1x000 framemask */
         switch (sel) {
         case 0:
-            gen_helper_mtc0_framemask(t0);
+            gen_helper_mtc0_framemask(arg);
             rn = "Framemask";
             break;
         default:
@@ -5018,32 +5020,32 @@
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_debug(t0); /* EJTAG support */
+            gen_helper_mtc0_debug(arg); /* EJTAG support */
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
             rn = "Debug";
             break;
         case 1:
-//            gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceControl";
 //            break;
         case 2:
-//            gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceControl2";
 //            break;
         case 3:
-//            gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
+//            gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "UserTraceData";
 //            break;
         case 4:
-//            gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
+//            gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceBPC";
@@ -5056,7 +5058,7 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
+            tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
             rn = "DEPC";
             break;
         default:
@@ -5066,35 +5068,35 @@
     case 25:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_performance0(t0);
+            gen_helper_mtc0_performance0(arg);
             rn = "Performance0";
             break;
         case 1:
-//            gen_helper_mtc0_performance1(t0);
+//            gen_helper_mtc0_performance1(arg);
             rn = "Performance1";
 //            break;
         case 2:
-//            gen_helper_mtc0_performance2(t0);
+//            gen_helper_mtc0_performance2(arg);
             rn = "Performance2";
 //            break;
         case 3:
-//            gen_helper_mtc0_performance3(t0);
+//            gen_helper_mtc0_performance3(arg);
             rn = "Performance3";
 //            break;
         case 4:
-//            gen_helper_mtc0_performance4(t0);
+//            gen_helper_mtc0_performance4(arg);
             rn = "Performance4";
 //            break;
         case 5:
-//            gen_helper_mtc0_performance5(t0);
+//            gen_helper_mtc0_performance5(arg);
             rn = "Performance5";
 //            break;
         case 6:
-//            gen_helper_mtc0_performance6(t0);
+//            gen_helper_mtc0_performance6(arg);
             rn = "Performance6";
 //            break;
         case 7:
-//            gen_helper_mtc0_performance7(t0);
+//            gen_helper_mtc0_performance7(arg);
             rn = "Performance7";
 //            break;
         default:
@@ -5121,14 +5123,14 @@
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taglo(t0);
+            gen_helper_mtc0_taglo(arg);
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datalo(t0);
+            gen_helper_mtc0_datalo(arg);
             rn = "DataLo";
             break;
         default:
@@ -5141,14 +5143,14 @@
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taghi(t0);
+            gen_helper_mtc0_taghi(arg);
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datahi(t0);
+            gen_helper_mtc0_datahi(arg);
             rn = "DataHi";
             break;
         default:
@@ -5159,7 +5161,7 @@
     case 30:
         switch (sel) {
         case 0:
-            tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+            tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
             rn = "ErrorEPC";
             break;
         default:
@@ -5170,7 +5172,7 @@
         switch (sel) {
         case 0:
             /* EJTAG support */
-            gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
+            gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
             rn = "DESAVE";
             break;
         default: