)]}'
{
  "commit": "d4dfb4ffd4008d0d7d3bc9b1dca3e5c5afcc4336",
  "tree": "0698706bb126f873d210e3750490639e76d91bbc",
  "parents": [
    "527dede083d3e3e5a13ee996776926e0a0c4e258"
  ],
  "author": {
    "name": "Troy Lee",
    "email": "troy_lee@aspeedtech.com",
    "time": "Mon Mar 17 14:59:37 2025 +0800"
  },
  "committer": {
    "name": "Cédric Le Goater",
    "email": "clg@redhat.com",
    "time": "Sun Mar 23 18:42:16 2025 +0100"
  },
  "message": "aspeed: Fix maximum number of spi controller\n\nCommit 6de4aa8dc544 (\"hw/arm/aspeed_ast27x0: Add SoC Support for AST2700\nA1\") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the\nmaximum number of spi controller to 2, result in ehci[0] is being\noverwritten in runtime.\n\nSigned-off-by: Troy Lee \u003ctroy_lee@aspeedtech.com\u003e\nFixes: 6de4aa8dc544 (\"hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1\")\nReviewed-by: Cédric Le Goater \u003cclg@redhat.com\u003e\nLink: https://lore.kernel.org/qemu-devel/20250317065938.1902272-1-troy_lee@aspeedtech.com\nSigned-off-by: Cédric Le Goater \u003cclg@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f899356ed94c5dc4fa3f0ca3fd8a3f6e9103c0af",
      "old_mode": 33188,
      "old_path": "include/hw/arm/aspeed_soc.h",
      "new_id": "f069d17d1629a98c287284b5afdbb3d581660a05",
      "new_mode": 33188,
      "new_path": "include/hw/arm/aspeed_soc.h"
    }
  ]
}