commit d37aca662561a54a5ea177c6c05280633fa41cb8
author pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Oct 22 11:54:30 2006 +0000
committer pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Oct 22 11:54:30 2006 +0000
tree 2ec3f81972d17571e8fb1b9b802270433c1173e1
parent e6e5906b6e0a81718066ca43aef57515026c6624

Fix comment typo.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2197 c046a42c-6fe2-441c-8c8c-71466251a162

target-arm/cpu.h

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 75a1f13..b994bdd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -48,7 +48,7 @@
     /* Regs for current mode.  */
     uint32_t regs[16];
     /* Frequently accessed CPSR bits are stored separately for efficiently.
-       This contains all the other bits.  Use cpsr_{read,write} to accless
+       This contains all the other bits.  Use cpsr_{read,write} to access
        the whole CPSR.  */
     uint32_t uncached_cpsr;
     uint32_t spsr;