)]}'
{
  "commit": "d359db00e6dfaf12cbdedd30e36f879110d4f9d1",
  "tree": "f1b4d414461d61fada01daacc59d2a29783af873",
  "parents": [
    "80189035de73f30e42a7f933c45cccfc4b0c56e9"
  ],
  "author": {
    "name": "Tom Musta",
    "email": "tommusta@gmail.com",
    "time": "Mon Mar 31 16:03:58 2014 -0500"
  },
  "committer": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Tue Apr 08 11:20:02 2014 +0200"
  },
  "message": "target-ppc: Correct LE Host Inversion of Lower VSRs\n\nThis change properly orders the doublewords of the VSRs 0-31.  Because these\nregisters are constructed from separate doublewords, they must be inverted\non Little Endian hosts.  The inversion is performed both when the VSR is read\nand when it is written.\n\nSigned-off-by: Tom Musta \u003ctommusta@gmail.com\u003e\nTested-by: Tom Musta \u003ctommusta@gmail.com\u003e\nSigned-off-by: Alexander Graf \u003cagraf@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d79aae9dbe9d2fd03c3e9870c08ba289d23e92b6",
      "old_mode": 33188,
      "old_path": "target-ppc/fpu_helper.c",
      "new_id": "9fc7dd8264fbf2b318bea4cb967fc1c982746aa5",
      "new_mode": 33188,
      "new_path": "target-ppc/fpu_helper.c"
    }
  ]
}