)]}' { "commit": "d35146a6606cf6ebb4e24bb97dfc0330f074f6e3", "tree": "6709d274b949ca566714f2a1e071e2c85ba36207", "parents": [ "3f8cd046c151c471d9a34181320f4a7d3f72b32a" ], "author": { "name": "Shameer Kolothum", "email": "skolothumtho@nvidia.com", "time": "Fri Aug 29 09:25:33 2025 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Tue Sep 16 17:31:55 2025 +0100" }, "message": "qtest/bios-tables-test: Update tables for smmuv3 tests\n\nFor the legacy smmuv3 test case, generated IORT has a single SMMUv3 node,\na Root Complex(RC) node and 1 ITS node.\nRC node features 4 ID mappings, of which 2 points to SMMU node and the\nremaining ones points to ITS.\n\n pcie.0 -\u003e {SMMU0} -\u003e {ITS}\n{RC} pcie.1 -\u003e {SMMU0} -\u003e {ITS}\n pcie.2 -\u003e {ITS}\n [all other ids] -\u003e {ITS}\n\n...\n[030h 0048 1] Type : 00\n[031h 0049 2] Length : 0018\n[033h 0051 1] Revision : 01\n[034h 0052 4] Identifier : 00000000\n[038h 0056 4] Mapping Count : 00000000\n[03Ch 0060 4] Mapping Offset : 00000000\n\n[040h 0064 4] ItsCount : 00000001\n[044h 0068 4] Identifiers : 00000000\n\n[048h 0072 1] Type : 04\n[049h 0073 2] Length : 0058\n[04Bh 0075 1] Revision : 04\n[04Ch 0076 4] Identifier : 00000001\n[050h 0080 4] Mapping Count : 00000001\n[054h 0084 4] Mapping Offset : 00000044\n\n[058h 0088 8] Base Address : 0000000009050000\n[060h 0096 4] Flags (decoded below) : 00000001\n COHACC Override : 1\n HTTU Override : 0\n Proximity Domain Valid : 0\n[064h 0100 4] Reserved : 00000000\n[068h 0104 8] VATOS Address : 0000000000000000\n[070h 0112 4] Model : 00000000\n[074h 0116 4] Event GSIV : 0000006A\n[078h 0120 4] PRI GSIV : 0000006B\n[07Ch 0124 4] GERR GSIV : 0000006D\n[080h 0128 4] Sync GSIV : 0000006C\n[084h 0132 4] Proximity Domain : 00000000\n[088h 0136 4] Device ID Mapping Index : 00000000\n\n[08Ch 0140 4] Input base : 00000000\n[090h 0144 4] ID Count : 0000FFFF\n[094h 0148 4] Output Base : 00000000\n[098h 0152 4] Output Reference : 00000030\n[09Ch 0156 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[0A0h 0160 1] Type : 02\n[0A1h 0161 2] Length : 0074\n[0A3h 0163 1] Revision : 03\n[0A4h 0164 4] Identifier : 00000002\n[0A8h 0168 4] Mapping Count : 00000004\n[0ACh 0172 4] Mapping Offset : 00000024\n\n[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties]\n[0B0h 0176 4] Cache Coherency : 00000001\n[0B4h 0180 1] Hints (decoded below) : 00\n Transient : 0\n Write Allocate : 0\n Read Allocate : 0\n Override : 0\n[0B5h 0181 2] Reserved : 0000\n[0B7h 0183 1] Memory Flags (decoded below) : 03\n Coherency : 1\n Device Attribute : 1\n[0B8h 0184 4] ATS Attribute : 00000000\n[0BCh 0188 4] PCI Segment Number : 00000000\n[0C0h 0192 1] Memory Size Limit : 40\n[0C1h 0193 2] PASID Capabilities : 0000\n[0C3h 0195 1] Reserved : 00\n\n[0C4h 0196 4] Input base : 00000000\n[0C8h 0200 4] ID Count : 000001FF\n[0CCh 0204 4] Output Base : 00000000\n[0D0h 0208 4] Output Reference : 00000048\n[0D4h 0212 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[0D8h 0216 4] Input base : 00001000\n[0DCh 0220 4] ID Count : 000000FF\n[0E0h 0224 4] Output Base : 00001000\n[0E4h 0228 4] Output Reference : 00000048\n[0E8h 0232 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[0ECh 0236 4] Input base : 00000200\n[0F0h 0240 4] ID Count : 00000DFF\n[0F4h 0244 4] Output Base : 00000200\n[0F8h 0248 4] Output Reference : 00000030\n[0FCh 0252 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[100h 0256 4] Input base : 00001100\n[104h 0260 4] ID Count : 0000EEFF\n[108h 0264 4] Output Base : 00001100\n[10Ch 0268 4] Output Reference : 00000030\n[110h 0272 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\nFor the smmuv3-dev test case, IORT has 2 SMMUV3 nodes,\n1 RC node and 1 ITS node.\nRC node features 4 ID mappings. 2 of them target the 2\nSMMU nodes while the others targets the ITS.\n\n pcie.0 -\u003e {SMMU0} -\u003e {ITS}\n{RC} pcie.1 -\u003e {SMMU1} -\u003e {ITS}\n pcie.2 -\u003e {ITS}\n [all other ids] -\u003e {ITS}\n...\n[030h 0048 1] Type : 00\n[031h 0049 2] Length : 0018\n[033h 0051 1] Revision : 01\n[034h 0052 4] Identifier : 00000000\n[038h 0056 4] Mapping Count : 00000000\n[03Ch 0060 4] Mapping Offset : 00000000\n\n[040h 0064 4] ItsCount : 00000001\n[044h 0068 4] Identifiers : 00000000\n\n[048h 0072 1] Type : 04\n[049h 0073 2] Length : 0058\n[04Bh 0075 1] Revision : 04\n[04Ch 0076 4] Identifier : 00000001\n[050h 0080 4] Mapping Count : 00000001\n[054h 0084 4] Mapping Offset : 00000044\n\n[058h 0088 8] Base Address : 000000000C000000\n[060h 0096 4] Flags (decoded below) : 00000001\n COHACC Override : 1\n HTTU Override : 0\n Proximity Domain Valid : 0\n[064h 0100 4] Reserved : 00000000\n[068h 0104 8] VATOS Address : 0000000000000000\n[070h 0112 4] Model : 00000000\n[074h 0116 4] Event GSIV : 00000090\n[078h 0120 4] PRI GSIV : 00000091\n[07Ch 0124 4] GERR GSIV : 00000093\n[080h 0128 4] Sync GSIV : 00000092\n[084h 0132 4] Proximity Domain : 00000000\n[088h 0136 4] Device ID Mapping Index : 00000000\n\n[08Ch 0140 4] Input base : 00000000\n[090h 0144 4] ID Count : 0000FFFF\n[094h 0148 4] Output Base : 00000000\n[098h 0152 4] Output Reference : 00000030\n[09Ch 0156 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[0A0h 0160 1] Type : 04\n[0A1h 0161 2] Length : 0058\n[0A3h 0163 1] Revision : 04\n[0A4h 0164 4] Identifier : 00000002\n[0A8h 0168 4] Mapping Count : 00000001\n[0ACh 0172 4] Mapping Offset : 00000044\n\n[0B0h 0176 8] Base Address : 000000000C020000\n[0B8h 0184 4] Flags (decoded below) : 00000001\n COHACC Override : 1\n HTTU Override : 0\n Proximity Domain Valid : 0\n[0BCh 0188 4] Reserved : 00000000\n[0C0h 0192 8] VATOS Address : 0000000000000000\n[0C8h 0200 4] Model : 00000000\n[0CCh 0204 4] Event GSIV : 00000094\n[0D0h 0208 4] PRI GSIV : 00000095\n[0D4h 0212 4] GERR GSIV : 00000097\n[0D8h 0216 4] Sync GSIV : 00000096\n[0DCh 0220 4] Proximity Domain : 00000000\n[0E0h 0224 4] Device ID Mapping Index : 00000000\n\n[0E4h 0228 4] Input base : 00000000\n[0E8h 0232 4] ID Count : 0000FFFF\n[0ECh 0236 4] Output Base : 00000000\n[0F0h 0240 4] Output Reference : 00000030\n[0F4h 0244 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[0F8h 0248 1] Type : 02\n[0F9h 0249 2] Length : 0074\n[0FBh 0251 1] Revision : 03\n[0FCh 0252 4] Identifier : 00000003\n[100h 0256 4] Mapping Count : 00000004\n[104h 0260 4] Mapping Offset : 00000024\n\n[108h 0264 8] Memory Properties : [IORT Memory Access Properties]\n[108h 0264 4] Cache Coherency : 00000001\n[10Ch 0268 1] Hints (decoded below) : 00\n Transient : 0\n Write Allocate : 0\n Read Allocate : 0\n Override : 0\n[10Dh 0269 2] Reserved : 0000\n[10Fh 0271 1] Memory Flags (decoded below) : 03\n Coherency : 1\n Device Attribute : 1\n[110h 0272 4] ATS Attribute : 00000000\n[114h 0276 4] PCI Segment Number : 00000000\n[118h 0280 1] Memory Size Limit : 40\n[119h 0281 2] PASID Capabilities : 0000\n[11Bh 0283 1] Reserved : 00\n\n[11Ch 0284 4] Input base : 00000000\n[120h 0288 4] ID Count : 000001FF\n[124h 0292 4] Output Base : 00000000\n[128h 0296 4] Output Reference : 00000048\n[12Ch 0300 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[130h 0304 4] Input base : 00001000\n[134h 0308 4] ID Count : 000000FF\n[138h 0312 4] Output Base : 00001000\n[13Ch 0316 4] Output Reference : 000000A0\n[140h 0320 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[144h 0324 4] Input base : 00000200\n[148h 0328 4] ID Count : 00000DFF\n[14Ch 0332 4] Output Base : 00000200\n[150h 0336 4] Output Reference : 00000030\n[154h 0340 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\n[158h 0344 4] Input base : 00001100\n[15Ch 0348 4] ID Count : 0000EEFF\n[160h 0352 4] Output Base : 00001100\n[164h 0356 4] Output Reference : 00000030\n[168h 0360 4] Flags (decoded below) : 00000000\n Single Mapping : 0\n\nNote: DSDT changes are not described here as it is not impacted by the\nway the SMMUv3 is instantiated.\n\nReviewed-by: Jonathan Cameron \u003cjonathan.cameron@huawei.com\u003e\nReviewed-by: Eric Auger \u003ceric.auger@redhat.com\u003e\nTested-by: Eric Auger \u003ceric.auger@redhat.com\u003e\nTested-by: Nicolin Chen \u003cnicolinc@nvidia.com\u003e\nSigned-off-by: Shameer Kolothum \u003cshameerali.kolothum.thodi@huawei.com\u003e\nSigned-off-by: Shameer Kolothum \u003cskolothumtho@nvidia.com\u003e\nReviewed-by: Donald Dutile \u003cddutile@redhat.com\u003e\nReviewed-by: Nicolin Chen \u003cnicolinc@nvidia.com\u003e\nMessage-id: 20250829082543.7680-12-skolothumtho@nvidia.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "e69de29bb2d1d6434b8b29ae775ad8c2e48c5391", "old_mode": 33188, "old_path": "tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev", "new_id": "53d4c07f423886d8c4b57f1da6498eef5a08b556", "new_mode": 33188, "new_path": "tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev" }, { "type": "modify", "old_id": "e69de29bb2d1d6434b8b29ae775ad8c2e48c5391", "old_mode": 33188, "old_path": "tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy", "new_id": "53d4c07f423886d8c4b57f1da6498eef5a08b556", "new_mode": 33188, "new_path": "tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy" }, { "type": "modify", "old_id": "e69de29bb2d1d6434b8b29ae775ad8c2e48c5391", "old_mode": 33188, "old_path": "tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", "new_id": "67be268f62afbf2d9459540984da5e9340afdaaa", "new_mode": 33188, "new_path": "tests/data/acpi/aarch64/virt/IORT.smmuv3-dev" }, { "type": "modify", "old_id": "e69de29bb2d1d6434b8b29ae775ad8c2e48c5391", "old_mode": 33188, "old_path": "tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", "new_id": "41981a449fc306b80cccd87ddec3c593a8d72c07", "new_mode": 33188, "new_path": "tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy" }, { "type": "modify", "old_id": "2e3e3ccdcec2e583d8e17212ac132e866c27ea02", "old_mode": 33188, "old_path": "tests/qtest/bios-tables-test-allowed-diff.h", "new_id": "dfb8523c8bf457c471cea8d860eff394b2d3700f", "new_mode": 33188, "new_path": "tests/qtest/bios-tables-test-allowed-diff.h" } ] }