)]}'
{
  "commit": "d2c5759c8dd4c00195d4ebecc7d009e41df6baef",
  "tree": "d7800db6218c2f4578582a0a720118dab9778393",
  "parents": [
    "86c78b280607fcff787866a03374047c65037a90"
  ],
  "author": {
    "name": "Deepak Gupta",
    "email": "debug@rivosinc.com",
    "time": "Wed Mar 05 22:46:36 2025 -0800"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Wed Mar 19 16:34:32 2025 +1000"
  },
  "message": "target/riscv: fixes a bug against `ssamoswap` behavior in M-mode\n\nCommit f06bfe3dc38c (\"target/riscv: implement zicfiss instructions\") adds\n`ssamoswap` instruction. `ssamoswap` takes the code-point from existing\nreserved encoding (and not a zimop like other shadow stack instructions).\nIf shadow stack is not enabled (via xenvcfg.SSE) and effective priv is\nless than M then `ssamoswap` must result in an illegal instruction\nexception. However if effective priv is M, then `ssamoswap` results in\nstore/AMO access fault. See Section \"22.2.3. Shadow Stack Memory\nProtection\" of priv spec.\n\nFixes: f06bfe3dc38c (\"target/riscv: implement zicfiss instructions\")\n\nReported-by: Ved Shanbhogue \u003cved@rivosinc.com\u003e\nSigned-off-by: Deepak Gupta \u003cdebug@rivosinc.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20250306064636.452396-2-debug@rivosinc.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e3ebc4977c5b09b433ca6537ce0576d2ce78d5c7",
      "old_mode": 33188,
      "old_path": "target/riscv/insn_trans/trans_rvzicfiss.c.inc",
      "new_id": "b0096adcd0e50a6c2c513500b8a571f62369e160",
      "new_mode": 33188,
      "new_path": "target/riscv/insn_trans/trans_rvzicfiss.c.inc"
    }
  ]
}