)]}'
{
  "commit": "d29f3f5cddb2614b3eebe216cce59ef9350db0a0",
  "tree": "c335f0a1f7de3df97ed9a8696aa7c91a6db2c810",
  "parents": [
    "da5cafdc4dddc9e69983b99f01c8eb43a8140929"
  ],
  "author": {
    "name": "Davidlohr Bueso",
    "email": "dave@stgolabs.net",
    "time": "Wed Feb 04 17:09:29 2026 +0000"
  },
  "committer": {
    "name": "Michael S. Tsirkin",
    "email": "mst@redhat.com",
    "time": "Fri Feb 20 13:04:45 2026 -0500"
  },
  "message": "hw/pcie: Support enabling flit mode\n\nPCIe Flit Mode, introduced with the PCIe 6.0 specification, is a\nfundamental change in how data is transmitted over the bus to\nimprove transfer rates. It shifts from variable-sized Transaction\nLayer Packets (TLPs) to fixed 256-byte Flow Control Units (FLITs).\n\nAs with the link speed and width training, have ad-hoc property for\nsetting the flit mode and allow CXL components to make use of it.\n\nFor the CXL root port and dsp cases, always report flit mode but\nthe actual value after \u0027training\u0027 will depend on the downstream\ndevice configuration.\n\nSuggested-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nTested-by: Dongjoo Seo \u003cdongjoo.seo1@samsung.com\u003e\nSigned-off-by: Davidlohr Bueso \u003cdave@stgolabs.net\u003e\nSigned-off-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nReviewed-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nMessage-Id: \u003c20260204170936.43959-2-Jonathan.Cameron@huawei.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "10ad3b8b59cb5fc9271fafb464c409c6bc88e7b4",
      "old_mode": 33188,
      "old_path": "hw/mem/cxl_type3.c",
      "new_id": "328322b1efb235a7cd2471bf2b77ef399c7fb3ed",
      "new_mode": 33188,
      "new_path": "hw/mem/cxl_type3.c"
    },
    {
      "type": "modify",
      "old_id": "f7b131e67e8eaf939841f728d8ba8aabca690773",
      "old_mode": 33188,
      "old_path": "hw/pci-bridge/cxl_downstream.c",
      "new_id": "64086d8ec2f2675b2b5ab0d3534b402db2d1f0d0",
      "new_mode": 33188,
      "new_path": "hw/pci-bridge/cxl_downstream.c"
    },
    {
      "type": "modify",
      "old_id": "197d3148d201028aa3cc1875b968e11b387f8a70",
      "old_mode": 33188,
      "old_path": "hw/pci-bridge/cxl_root_port.c",
      "new_id": "5641048084a4aac417f5ecc10522ed127e9ae54d",
      "new_mode": 33188,
      "new_path": "hw/pci-bridge/cxl_root_port.c"
    },
    {
      "type": "modify",
      "old_id": "6d708fadc25353f2d045b0a459f9387df59f1738",
      "old_mode": 33188,
      "old_path": "hw/pci-bridge/cxl_upstream.c",
      "new_id": "c352d11dc7b7b9cd875de4a7a6f0545f2be36396",
      "new_mode": 33188,
      "new_path": "hw/pci-bridge/cxl_upstream.c"
    },
    {
      "type": "modify",
      "old_id": "50fc4aa8eb12b6abd90c363c95d7f5dbb90a8f87",
      "old_mode": 33188,
      "old_path": "hw/pci/pcie.c",
      "new_id": "cae5061e69ce05ff3882c52f5de029440d7a0a97",
      "new_mode": 33188,
      "new_path": "hw/pci/pcie.c"
    },
    {
      "type": "modify",
      "old_id": "d5906afb19a5e596597afe2e35a78331b848c8c8",
      "old_mode": 33188,
      "old_path": "include/hw/cxl/cxl_device.h",
      "new_id": "7d9236db8c85e6bf96abe6580cd9917a746d46e4",
      "new_mode": 33188,
      "new_path": "include/hw/cxl/cxl_device.h"
    },
    {
      "type": "modify",
      "old_id": "f208397ffe962c5ff673944f9a88009ecad6a47f",
      "old_mode": 33188,
      "old_path": "include/hw/pci-bridge/cxl_upstream_port.h",
      "new_id": "e3d6a27acc86695b42b712ccd19b5ec55e6c2209",
      "new_mode": 33188,
      "new_path": "include/hw/pci-bridge/cxl_upstream_port.h"
    },
    {
      "type": "modify",
      "old_id": "d4e065db82863f36a758a0318bc272411e25bff3",
      "old_mode": 33188,
      "old_path": "include/hw/pci/pcie.h",
      "new_id": "71ba94874b4bd684fd6110d7baeedbbdc3bf26d6",
      "new_mode": 33188,
      "new_path": "include/hw/pci/pcie.h"
    },
    {
      "type": "modify",
      "old_id": "7cd7af8cfa4bd3f79b483b65ec8adc43238444a6",
      "old_mode": 33188,
      "old_path": "include/hw/pci/pcie_port.h",
      "new_id": "53cd64c5edff6713b85dc53f4d9f97676f247332",
      "new_mode": 33188,
      "new_path": "include/hw/pci/pcie_port.h"
    }
  ]
}