commit d108609bf9ba160d2e2044ce7d553f691ac96dbd
author Peter Maydell <peter.maydell@linaro.org> Mon Mar 24 15:59:02 2014 +0000
committer Peter Maydell <peter.maydell@linaro.org> Mon Mar 24 16:34:01 2014 +0000
tree f04b92c7a59fcab6825406e9dc608b2e48ae7308
parent 3a87f8b6859e6221b827ab4737779dddb37553ec

target-arm: Fix A64 Neon MLS

The order of operands for the accumulate step in disas_simd_3same_int()
was reversed. This only affected the MLS instruction, since all the
other accumulating instructions in this category perform an addition
rather than a subtraction.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target-arm/translate-a64.c

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f06450..9175e48 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8925,7 +8925,7 @@
 
                 genfn = fns[size][is_sub];
                 read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
-                genfn(tcg_res, tcg_res, tcg_op1);
+                genfn(tcg_res, tcg_op1, tcg_res);
             }
 
             write_vec_element_i32(s, tcg_res, rd, pass, MO_32);