hw/arm/sysbus-fdt: enable amd-xgbe dynamic instantiation
This patch allows the instantiation of the vfio-amd-xgbe device
from the QEMU command line (-device vfio-amd-xgbe,host="<device>").
The guest is exposed with a device tree node that combines the description
of both XGBE and PHY (representation supported from 4.2 onwards kernel):
Documentation/devicetree/bindings/net/amd-xgbe.txt.
There are 5 register regions, 6 interrupts including 4 optional
edge-sensitive per-channel interrupts.
Some property values are inherited from host device tree. Host device tree
must feature a combined XGBE/PHY representation (>= 4.2 host kernel).
2 clock nodes (dma and ptp) also are created. It is checked those clocks
are fixed on host side.
AMD XGBE node creation function has a dependency on vfio Linux header and
more generally node creation function for VFIO platform devices only make
sense with CONFIG_LINUX so let's protect this code with #ifdef CONFIG_LINUX.
Signed-off-by: Eric Auger <eric.auger@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
diff --git a/hw/arm/sysbus-fdt.c b/hw/arm/sysbus-fdt.c
index 8575cfe..9920388 100644
--- a/hw/arm/sysbus-fdt.c
+++ b/hw/arm/sysbus-fdt.c
@@ -23,6 +23,10 @@
#include "qemu/osdep.h"
#include <libfdt.h>
+#include "qemu-common.h"
+#ifdef CONFIG_LINUX
+#include <linux/vfio.h>
+#endif
#include "hw/arm/sysbus-fdt.h"
#include "qemu/error-report.h"
#include "sysemu/device_tree.h"
@@ -30,6 +34,7 @@
#include "sysemu/sysemu.h"
#include "hw/vfio/vfio-platform.h"
#include "hw/vfio/vfio-calxeda-xgmac.h"
+#include "hw/vfio/vfio-amd-xgbe.h"
#include "hw/arm/fdt.h"
/*
@@ -65,6 +70,8 @@
bool optional;
} HostProperty;
+#ifdef CONFIG_LINUX
+
/**
* copy_properties_from_host
*
@@ -127,12 +134,9 @@
* @host_phandle: phandle of the clock in host device tree
* @guest_phandle: phandle to assign to the guest node
*/
-void fdt_build_clock_node(void *host_fdt, void *guest_fdt,
- uint32_t host_phandle,
- uint32_t guest_phandle);
-void fdt_build_clock_node(void *host_fdt, void *guest_fdt,
- uint32_t host_phandle,
- uint32_t guest_phandle)
+static void fdt_build_clock_node(void *host_fdt, void *guest_fdt,
+ uint32_t host_phandle,
+ uint32_t guest_phandle)
{
char *node_path = NULL;
char *nodename;
@@ -177,6 +181,28 @@
g_free(node_path);
}
+/**
+ * sysfs_to_dt_name: convert the name found in sysfs into the node name
+ * for instance e0900000.xgmac is converted into xgmac@e0900000
+ * @sysfs_name: directory name in sysfs
+ *
+ * returns the device tree name upon success or NULL in case the sysfs name
+ * does not match the expected format
+ */
+static char *sysfs_to_dt_name(const char *sysfs_name)
+{
+ gchar **substrings = g_strsplit(sysfs_name, ".", 2);
+ char *dt_name = NULL;
+
+ if (!substrings || !substrings[0] || !substrings[1]) {
+ goto out;
+ }
+ dt_name = g_strdup_printf("%s@%s", substrings[1], substrings[0]);
+out:
+ g_strfreev(substrings);
+ return dt_name;
+}
+
/* Device Specific Code */
/**
@@ -244,9 +270,165 @@
return ret;
}
+/* AMD xgbe properties whose values are copied/pasted from host */
+static HostProperty amd_xgbe_copied_properties[] = {
+ {"compatible", false},
+ {"dma-coherent", true},
+ {"amd,per-channel-interrupt", true},
+ {"phy-mode", false},
+ {"mac-address", true},
+ {"amd,speed-set", false},
+ {"amd,serdes-blwc", true},
+ {"amd,serdes-cdr-rate", true},
+ {"amd,serdes-pq-skew", true},
+ {"amd,serdes-tx-amp", true},
+ {"amd,serdes-dfe-tap-config", true},
+ {"amd,serdes-dfe-tap-enable", true},
+ {"clock-names", false},
+};
+
+/**
+ * add_amd_xgbe_fdt_node
+ *
+ * Generates the combined xgbe/phy node following kernel >=4.2
+ * binding documentation:
+ * Documentation/devicetree/bindings/net/amd-xgbe.txt:
+ * Also 2 clock nodes are created (dma and ptp)
+ *
+ * Asserts in case of error
+ */
+static int add_amd_xgbe_fdt_node(SysBusDevice *sbdev, void *opaque)
+{
+ PlatformBusFDTData *data = opaque;
+ PlatformBusDevice *pbus = data->pbus;
+ VFIOPlatformDevice *vdev = VFIO_PLATFORM_DEVICE(sbdev);
+ VFIODevice *vbasedev = &vdev->vbasedev;
+ VFIOINTp *intp;
+ const char *parent_node = data->pbus_node_name;
+ char **node_path, *nodename, *dt_name;
+ void *guest_fdt = data->fdt, *host_fdt;
+ const void *r;
+ int i, prop_len;
+ uint32_t *irq_attr, *reg_attr, *host_clock_phandles;
+ uint64_t mmio_base, irq_number;
+ uint32_t guest_clock_phandles[2];
+
+ host_fdt = load_device_tree_from_sysfs();
+
+ dt_name = sysfs_to_dt_name(vbasedev->name);
+ if (!dt_name) {
+ error_setg(&error_fatal, "%s incorrect sysfs device name %s",
+ __func__, vbasedev->name);
+ }
+ node_path = qemu_fdt_node_path(host_fdt, dt_name, vdev->compat,
+ &error_fatal);
+ if (!node_path || !node_path[0]) {
+ error_setg(&error_fatal, "%s unable to retrieve node path for %s/%s",
+ __func__, dt_name, vdev->compat);
+ }
+
+ if (node_path[1]) {
+ error_setg(&error_fatal, "%s more than one node matching %s/%s!",
+ __func__, dt_name, vdev->compat);
+ }
+
+ g_free(dt_name);
+
+ if (vbasedev->num_regions != 5) {
+ error_setg(&error_fatal, "%s Does the host dt node combine XGBE/PHY?",
+ __func__);
+ }
+
+ /* generate nodes for DMA_CLK and PTP_CLK */
+ r = qemu_fdt_getprop(host_fdt, node_path[0], "clocks",
+ &prop_len, &error_fatal);
+ if (prop_len != 8) {
+ error_setg(&error_fatal, "%s clocks property should contain 2 handles",
+ __func__);
+ }
+ host_clock_phandles = (uint32_t *)r;
+ guest_clock_phandles[0] = qemu_fdt_alloc_phandle(guest_fdt);
+ guest_clock_phandles[1] = qemu_fdt_alloc_phandle(guest_fdt);
+
+ /**
+ * clock handles fetched from host dt are in be32 layout whereas
+ * rest of the code uses cpu layout. Also guest clock handles are
+ * in cpu layout.
+ */
+ fdt_build_clock_node(host_fdt, guest_fdt,
+ be32_to_cpu(host_clock_phandles[0]),
+ guest_clock_phandles[0]);
+
+ fdt_build_clock_node(host_fdt, guest_fdt,
+ be32_to_cpu(host_clock_phandles[1]),
+ guest_clock_phandles[1]);
+
+ /* combined XGBE/PHY node */
+ mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
+ nodename = g_strdup_printf("%s/%s@%" PRIx64, parent_node,
+ vbasedev->name, mmio_base);
+ qemu_fdt_add_subnode(guest_fdt, nodename);
+
+ copy_properties_from_host(amd_xgbe_copied_properties,
+ ARRAY_SIZE(amd_xgbe_copied_properties),
+ host_fdt, guest_fdt,
+ node_path[0], nodename);
+
+ qemu_fdt_setprop_cells(guest_fdt, nodename, "clocks",
+ guest_clock_phandles[0],
+ guest_clock_phandles[1]);
+
+ reg_attr = g_new(uint32_t, vbasedev->num_regions * 2);
+ for (i = 0; i < vbasedev->num_regions; i++) {
+ mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, i);
+ reg_attr[2 * i] = cpu_to_be32(mmio_base);
+ reg_attr[2 * i + 1] = cpu_to_be32(
+ memory_region_size(&vdev->regions[i]->mem));
+ }
+ qemu_fdt_setprop(guest_fdt, nodename, "reg", reg_attr,
+ vbasedev->num_regions * 2 * sizeof(uint32_t));
+
+ irq_attr = g_new(uint32_t, vbasedev->num_irqs * 3);
+ for (i = 0; i < vbasedev->num_irqs; i++) {
+ irq_number = platform_bus_get_irqn(pbus, sbdev , i)
+ + data->irq_start;
+ irq_attr[3 * i] = cpu_to_be32(GIC_FDT_IRQ_TYPE_SPI);
+ irq_attr[3 * i + 1] = cpu_to_be32(irq_number);
+ /*
+ * General device interrupt and PCS auto-negotiation interrupts are
+ * level-sensitive while the 4 per-channel interrupts are edge
+ * sensitive
+ */
+ QLIST_FOREACH(intp, &vdev->intp_list, next) {
+ if (intp->pin == i) {
+ break;
+ }
+ }
+ if (intp->flags & VFIO_IRQ_INFO_AUTOMASKED) {
+ irq_attr[3 * i + 2] = cpu_to_be32(GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ } else {
+ irq_attr[3 * i + 2] = cpu_to_be32(GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
+ }
+ }
+ qemu_fdt_setprop(guest_fdt, nodename, "interrupts",
+ irq_attr, vbasedev->num_irqs * 3 * sizeof(uint32_t));
+
+ g_free(host_fdt);
+ g_strfreev(node_path);
+ g_free(irq_attr);
+ g_free(reg_attr);
+ g_free(nodename);
+ return 0;
+}
+
+#endif /* CONFIG_LINUX */
+
/* list of supported dynamic sysbus devices */
static const NodeCreationPair add_fdt_node_functions[] = {
+#ifdef CONFIG_LINUX
{TYPE_VFIO_CALXEDA_XGMAC, add_calxeda_midway_xgmac_fdt_node},
+ {TYPE_VFIO_AMD_XGBE, add_amd_xgbe_fdt_node},
+#endif
{"", NULL}, /* last element */
};
