target-cris: add v17 CPU
In the CRIS v17 CPU an ADDC (add with carry) instruction has been added
compared to the v10 instruction set.
Assembler syntax:
ADDC [Rs],Rd
ADDC [Rs+],Rd
Size: Dword
Description:
The source data is added together with the carry flag to the
destination register. The size of the operation is dword.
Operation:
Rd += s + C-flag;
Flags affected:
S R P U I X N Z V C
- - - - - 0 * * * *
Instruction format: ADDC [Rs],Rd
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Instruction format: ADDC [Rs+],Rd
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
[EI: Shorten 80+ lines]
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
diff --git a/target-cris/crisv10-decode.h b/target-cris/crisv10-decode.h
index 587fbdd..bdb4b6d 100644
--- a/target-cris/crisv10-decode.h
+++ b/target-cris/crisv10-decode.h
@@ -92,6 +92,7 @@
#define CRISV10_IND_JUMP_M 4
#define CRISV10_IND_DIP 5
#define CRISV10_IND_JUMP_R 6
+#define CRISV17_IND_ADDC 6
#define CRISV10_IND_BOUND 7
#define CRISV10_IND_BCC_M 7
#define CRISV10_IND_MOVE_M_SPR 8
