commit cead7fa4c06087c86c67c5ce815cc1ff0bfeac3a
author Richard Henderson <richard.henderson@linaro.org> Wed Nov 02 16:47:06 2022 +1100
committer Peter Maydell <peter.maydell@linaro.org> Fri Nov 04 10:58:58 2022 +0000
tree 8db40032d3744acdf1e549ad1eb201a2a5499a46
parent 638d5dbd78ea81c943959e2f2c65c109e5278a78

target/arm: Two fixes for secure ptw

Reversed the sense of non-secure in get_phys_addr_lpae,
and failed to initialize attrs.secure for ARMMMUIdx_Phys_S.

Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/ptw.c

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index e04dccf..3745ac9 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1381,7 +1381,7 @@
     descaddr |= (address >> (stride * (4 - level))) & indexmask;
     descaddr &= ~7ULL;
     nstable = extract32(tableattrs, 4, 1);
-    if (!nstable) {
+    if (nstable) {
         /*
          * Stage2_S -> Stage2 or Phys_S -> Phys_NS
          * Assert that the non-secure idx are even, and relative order.
@@ -2695,6 +2695,13 @@
     bool is_secure = ptw->in_secure;
     ARMMMUIdx s1_mmu_idx;
 
+    /*
+     * The page table entries may downgrade secure to non-secure, but
+     * cannot upgrade an non-secure translation regime's attributes
+     * to secure.
+     */
+    result->f.attrs.secure = is_secure;
+
     switch (mmu_idx) {
     case ARMMMUIdx_Phys_S:
     case ARMMMUIdx_Phys_NS:
@@ -2736,12 +2743,6 @@
         break;
     }
 
-    /*
-     * The page table entries may downgrade secure to non-secure, but
-     * cannot upgrade an non-secure translation regime's attributes
-     * to secure.
-     */
-    result->f.attrs.secure = is_secure;
     result->f.attrs.user = regime_is_user(env, mmu_idx);
 
     /*