)]}'
{
  "commit": "cdfd14e86ab0b1ca29a702d13a8e4af2e902a9bf",
  "tree": "3314c60de44742421a68119e0328ac2e4b1cafef",
  "parents": [
    "b623d803dda805f07aadcbf098961fde27315c19"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue Jun 11 16:39:51 2019 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Jun 13 15:14:06 2019 +0100"
  },
  "message": "target/arm: Convert the VCVT-to-f16 insns to decodetree\n\nConvert the VCVTT and VCVTB instructions which convert from\nf32 and f64 to f16 to decodetree.\n\nSince we\u0027re no longer constrained to the old decoder\u0027s style\nusing cpu_F0s and cpu_F0d we can perform a direct 16 bit\nstore of the right half of the input single-precision register\nrather than doing a load/modify/store sequence on the full\n32 bits.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "732bf6020a9db4b32e1c7738fe33519f7e180f5a",
      "old_mode": 33188,
      "old_path": "target/arm/translate-vfp.inc.c",
      "new_id": "a19ede867194fd11c64916b7364f460fd9a72184",
      "new_mode": 33188,
      "new_path": "target/arm/translate-vfp.inc.c"
    },
    {
      "type": "modify",
      "old_id": "f22b8ddf68a3236364188af5d9d0dd721ee088a6",
      "old_mode": 33188,
      "old_path": "target/arm/translate.c",
      "new_id": "b53bf93382795e44d0309884d59b31f8369a2829",
      "new_mode": 33188,
      "new_path": "target/arm/translate.c"
    },
    {
      "type": "modify",
      "old_id": "53d9544f7cdd23c41a73e02a9bb001af0aa8d20d",
      "old_mode": 33188,
      "old_path": "target/arm/vfp.decode",
      "new_id": "b88d1d06f02daf6486c844f25fccc99cb84c2f9d",
      "new_mode": 33188,
      "new_path": "target/arm/vfp.decode"
    }
  ]
}