commit cdc46fab07a122dfcc8a1054510a68d936ae3440
author Leon Alrae <leon.alrae@imgtec.com> Mon Jun 27 16:19:12 2016 +0100
committer Leon Alrae <leon.alrae@imgtec.com> Tue Jul 12 09:10:21 2016 +0100
tree ffe2e267d1bb1564ddb969998dd48fae3df322c6
parent a0c8060841f2d56fb3504292c18522b957972e4c

target-mips: enable 10-bit ASIDs in I6400 CPU

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

target-mips/translate_init.c

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c43bdb7..39ed5c4 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -685,7 +685,7 @@
                        (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
                        (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
-                       (0xfc << CP0C4_KScrExist),
+                       (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
                        (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
         .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |